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theotherjimmytheotherjimmy
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Merge pull request #5140 from ARMmbed/release-candidate
Release candidate for mbed-os-5.6.0-rc2
2 parents 411b7fd + de0e99c commit 6e08748

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37 files changed

+526
-86
lines changed

37 files changed

+526
-86
lines changed

‎features/FEATURE_LWIP/TESTS/mbedmicro-net/tcp_hello_world/main.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ using namespace utest::v1;
3333

3434
namespace {
3535
// Test connection information
36-
const char *HTTP_SERVER_NAME = "developer.mbed.org";
36+
const char *HTTP_SERVER_NAME = "os.mbed.com";
3737
const char *HTTP_SERVER_FILE_PATH = "/media/uploads/mbed_official/hello.txt";
3838
const int HTTP_SERVER_PORT = 80;
3939
#if defined(TARGET_VK_RZ_A1H)

‎features/FEATURE_LWIP/lwip-interface/mbed_lib.json‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -84,5 +84,10 @@
8484
"help": "Thread stack size for PPP",
8585
"value": 768
8686
}
87+
},
88+
"target_overrides": {
89+
"REALTEK_RTL8195AM": {
90+
"tcpip-thread-stacksize": 1600
91+
}
8792
}
8893
}

‎features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,7 @@ static void CMT_URC(ATCmdParser *at)
141141

142142
static bool set_atd(ATCmdParser *at)
143143
{
144-
bool success = at->send("ATD*99***" CTX"#") && at->recv("CONNECT");
144+
bool success = at->send("ATD*99***" CTX "#") && at->recv("CONNECT");
145145

146146
return success;
147147
}
@@ -469,7 +469,7 @@ nsapi_error_t PPPCellularInterface::setup_context_and_credentials()
469469
#endif
470470
success = _at->send("AT"
471471
"+FCLASS=0;" // set to connection (ATD) to data mode
472-
"+CGDCONT=" CTX",\"%s\",\"%s%s\"",
472+
"+CGDCONT=" CTX ",\"%s\",\"%s%s\"",
473473
pdp_type, auth, _apn
474474
)
475475
&& _at->recv("OK");

‎rtos/TARGET_CORTEX/mbed_rtx_idle.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -195,6 +195,14 @@ static void default_idle_hook(void)
195195
core_util_critical_section_exit();
196196
}
197197

198+
#elif defined(FEATURE_UVISOR)
199+
200+
static void default_idle_hook(void)
201+
{
202+
/* uVisor can't sleep. See <https://github.com/ARMmbed/uvisor/issues/420>
203+
* for details. */
204+
}
205+
198206
#else
199207

200208
static void default_idle_hook(void)

‎rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_ARM/irq_armv8mbl.S‎

Lines changed: 298 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,298 @@
1+
;/*
2+
; * Copyright (c) 2016-2017 ARM Limited. All rights reserved.
3+
; *
4+
; * SPDX-License-Identifier: Apache-2.0
5+
; *
6+
; * Licensed under the Apache License, Version 2.0 (the License); you may
7+
; * not use this file except in compliance with the License.
8+
; * You may obtain a copy of the License at
9+
; *
10+
; * www.apache.org/licenses/LICENSE-2.0
11+
; *
12+
; * Unless required by applicable law or agreed to in writing, software
13+
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14+
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15+
; * See the License for the specific language governing permissions and
16+
; * limitations under the License.
17+
; *
18+
; * -----------------------------------------------------------------------------
19+
; *
20+
; * Project: CMSIS-RTOS RTX
21+
; * Title: ARMv8M Baseline Exception handlers
22+
; *
23+
; * -----------------------------------------------------------------------------
24+
; */
25+
26+
I_T_RUN_OFS EQU 28 ; osInfo.thread.run offset
27+
TCB_SM_OFS EQU 48 ; TCB.stack_mem offset
28+
TCB_SP_OFS EQU 56 ; TCB.SP offset
29+
TCB_SF_OFS EQU 34 ; TCB.stack_frame offset
30+
TCB_TZM_OFS EQU 64 ; TCB.tz_memory offset
31+
32+
33+
PRESERVE8
34+
THUMB
35+
36+
37+
AREA |.constdata|, DATA, READONLY
38+
EXPORT irqRtxLib
39+
irqRtxLib DCB 0 ; Non weak library reference
40+
41+
42+
AREA |.text|, CODE, READONLY
43+
44+
45+
SVC_Handler PROC
46+
EXPORT SVC_Handler
47+
IMPORT osRtxUserSVC
48+
IMPORT osRtxInfo
49+
#ifdef __DOMAIN_NS
50+
IMPORT TZ_LoadContext_S
51+
IMPORT TZ_StoreContext_S
52+
#endif
53+
54+
MRS R0,PSP ; Get PSP
55+
LDR R1,[R0,#24] ; Load saved PC from stack
56+
SUBS R1,R1,#2 ; Point to SVC instruction
57+
LDRB R1,[R1] ; Load SVC number
58+
CMP R1,#0
59+
BNE SVC_User ; Branch if not SVC 0
60+
61+
PUSH {R0,LR} ; Save PSP and EXC_RETURN
62+
LDM R0,{R0-R3} ; Load function parameters from stack
63+
BLX R7 ; Call service function
64+
POP {R2,R3} ; Restore PSP and EXC_RETURN
65+
STMIA R2!,{R0-R1} ; Store function return values
66+
MOV LR,R3 ; Set EXC_RETURN
67+
68+
SVC_Context
69+
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
70+
LDMIA R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
71+
CMP R1,R2 ; Check if thread switch is required
72+
BEQ SVC_Exit ; Branch when threads are the same
73+
74+
CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted
75+
76+
SVC_ContextSave
77+
#ifdef __DOMAIN_NS
78+
LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier
79+
CBZ R0,SVC_ContextSave1 ; Branch if there is no secure context
80+
PUSH {R1,R2,R3,R7} ; Save registers
81+
MOV R7,LR ; Get EXC_RETURN
82+
BL TZ_StoreContext_S ; Store secure context
83+
MOV LR,R7 ; Set EXC_RETURN
84+
POP {R1,R2,R3,R7} ; Restore registers
85+
#endif
86+
87+
SVC_ContextSave1
88+
MRS R0,PSP ; Get PSP
89+
SUBS R0,R0,#32 ; Adjust PSP
90+
STR R0,[R1,#TCB_SP_OFS] ; Store SP
91+
STMIA R0!,{R4-R7} ; Save R4..R7
92+
MOV R4,R8
93+
MOV R5,R9
94+
MOV R6,R10
95+
MOV R7,R11
96+
STMIA R0!,{R4-R7} ; Save R8..R11
97+
98+
SVC_ContextSave2
99+
MOV R0,LR ; Get EXC_RETURN
100+
ADDS R1,R1,#TCB_SF_OFS ; Adjust address
101+
STRB R0,[R1] ; Store stack frame information
102+
103+
SVC_ContextSwitch
104+
SUBS R3,R3,#8 ; Adjust address
105+
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
106+
107+
SVC_ContextRestore
108+
#ifdef __DOMAIN_NS
109+
LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier
110+
CBZ R0,SVC_ContextRestore1 ; Branch if there is no secure context
111+
PUSH {R2,R3} ; Save registers
112+
BL TZ_LoadContext_S ; Load secure context
113+
POP {R2,R3} ; Restore registers
114+
#endif
115+
116+
SVC_ContextRestore1
117+
MOV R1,R2
118+
ADDS R1,R1,#TCB_SF_OFS ; Adjust address
119+
LDRB R0,[R1] ; Load stack frame information
120+
MOVS R1,#0xFF
121+
MVNS R1,R1 ; R1=0xFFFFFF00
122+
ORRS R0,R1
123+
MOV LR,R0 ; Set EXC_RETURN
124+
125+
#ifdef __DOMAIN_NS
126+
LSLS R0,R0,#25 ; Check domain of interrupted thread
127+
BPL SVC_ContextRestore2 ; Branch if non-secure
128+
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
129+
MSR PSP,R0 ; Set PSP
130+
BX LR ; Exit from handler
131+
#else
132+
LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base
133+
MSR PSPLIM,R0 ; Set PSPLIM
134+
#endif
135+
136+
SVC_ContextRestore2
137+
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
138+
ADDS R0,R0,#16 ; Adjust address
139+
LDMIA R0!,{R4-R7} ; Restore R8..R11
140+
MOV R8,R4
141+
MOV R9,R5
142+
MOV R10,R6
143+
MOV R11,R7
144+
MSR PSP,R0 ; Set PSP
145+
SUBS R0,R0,#32 ; Adjust address
146+
LDMIA R0!,{R4-R7} ; Restore R4..R7
147+
148+
SVC_Exit
149+
BX LR ; Exit from handler
150+
151+
SVC_User
152+
PUSH {R4,LR} ; Save registers
153+
LDR R2,=osRtxUserSVC ; Load address of SVC table
154+
LDR R3,[R2] ; Load SVC maximum number
155+
CMP R1,R3 ; Check SVC number range
156+
BHI SVC_Done ; Branch if out of range
157+
158+
LSLS R1,R1,#2
159+
LDR R4,[R2,R1] ; Load address of SVC function
160+
161+
LDM R0,{R0-R3} ; Load function parameters from stack
162+
BLX R4 ; Call service function
163+
MRS R4,PSP ; Get PSP
164+
STR R0,[R4] ; Store function return value
165+
166+
SVC_Done
167+
POP {R4,PC} ; Return from handler
168+
169+
ALIGN
170+
ENDP
171+
172+
173+
PendSV_Handler PROC
174+
EXPORT PendSV_Handler
175+
IMPORT osRtxPendSV_Handler
176+
177+
PUSH {R0,LR} ; Save EXC_RETURN
178+
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
179+
POP {R0,R1} ; Restore EXC_RETURN
180+
MOV LR,R1 ; Set EXC_RETURN
181+
B Sys_Context
182+
183+
ALIGN
184+
ENDP
185+
186+
187+
SysTick_Handler PROC
188+
EXPORT SysTick_Handler
189+
IMPORT osRtxTick_Handler
190+
191+
PUSH {R0,LR} ; Save EXC_RETURN
192+
BL osRtxTick_Handler ; Call osRtxTick_Handler
193+
POP {R0,R1} ; Restore EXC_RETURN
194+
MOV LR,R1 ; Set EXC_RETURN
195+
B Sys_Context
196+
197+
ALIGN
198+
ENDP
199+
200+
201+
Sys_Context PROC
202+
EXPORT Sys_Context
203+
IMPORT osRtxInfo
204+
#ifdef __DOMAIN_NS
205+
IMPORT TZ_LoadContext_S
206+
IMPORT TZ_StoreContext_S
207+
#endif
208+
209+
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
210+
LDM R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
211+
CMP R1,R2 ; Check if thread switch is required
212+
BEQ Sys_ContextExit ; Branch when threads are the same
213+
214+
Sys_ContextSave
215+
#ifdef __DOMAIN_NS
216+
LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier
217+
CBZ R0,Sys_ContextSave1 ; Branch if there is no secure context
218+
PUSH {R1,R2,R3,R7} ; Save registers
219+
MOV R7,LR ; Get EXC_RETURN
220+
BL TZ_StoreContext_S ; Store secure context
221+
MOV LR,R7 ; Set EXC_RETURN
222+
POP {R1,R2,R3,R7} ; Restore registers
223+
LSLS R7,R7,#25 ; Check domain of interrupted thread
224+
BMI Sys_ContextSave1 ; Branch if secure
225+
MRS R0,PSP ; Get PSP
226+
STR R0,[R1,#TCB_SP_OFS] ; Store SP
227+
B Sys_ContextSave2
228+
#endif
229+
230+
Sys_ContextSave1
231+
MRS R0,PSP ; Get PSP
232+
SUBS R0,R0,#32 ; Adjust address
233+
STR R0,[R1,#TCB_SP_OFS] ; Store SP
234+
STMIA R0!,{R4-R7} ; Save R4..R7
235+
MOV R4,R8
236+
MOV R5,R9
237+
MOV R6,R10
238+
MOV R7,R11
239+
STMIA R0!,{R4-R7} ; Save R8..R11
240+
241+
Sys_ContextSave2
242+
MOV R0,LR ; Get EXC_RETURN
243+
ADDS R1,R1,#TCB_SF_OFS ; Adjust address
244+
STRB R0,[R1] ; Store stack frame information
245+
246+
Sys_ContextSwitch
247+
SUBS R3,R3,#8 ; Adjust address
248+
STR R2,[R3] ; osRtxInfo.run: curr = next
249+
250+
Sys_ContextRestore
251+
#ifdef __DOMAIN_NS
252+
LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier
253+
CBZ R0,Sys_ContextRestore1 ; Branch if there is no secure context
254+
PUSH {R2,R3} ; Save registers
255+
BL TZ_LoadContext_S ; Load secure context
256+
POP {R2,R3} ; Restore registers
257+
#endif
258+
259+
Sys_ContextRestore1
260+
MOV R1,R2
261+
ADDS R1,R1,#TCB_SF_OFS ; Adjust offset
262+
LDRB R0,[R1] ; Load stack frame information
263+
MOVS R1,#0xFF
264+
MVNS R1,R1 ; R1=0xFFFFFF00
265+
ORRS R0,R1
266+
MOV LR,R0 ; Set EXC_RETURN
267+
268+
#ifdef __DOMAIN_NS
269+
LSLS R0,R0,#25 ; Check domain of interrupted thread
270+
BPL Sys_ContextRestore2 ; Branch if non-secure
271+
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
272+
MSR PSP,R0 ; Set PSP
273+
BX LR ; Exit from handler
274+
#else
275+
LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base
276+
MSR PSPLIM,R0 ; Set PSPLIM
277+
#endif
278+
279+
Sys_ContextRestore2
280+
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
281+
ADDS R0,R0,#16 ; Adjust address
282+
LDMIA R0!,{R4-R7} ; Restore R8..R11
283+
MOV R8,R4
284+
MOV R9,R5
285+
MOV R10,R6
286+
MOV R11,R7
287+
MSR PSP,R0 ; Set PSP
288+
SUBS R0,R0,#32 ; Adjust address
289+
LDMIA R0!,{R4-R7} ; Restore R4..R7
290+
291+
Sys_ContextExit
292+
BX LR ; Exit from handler
293+
294+
ALIGN
295+
ENDP
296+
297+
298+
END

‎targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ LR_IROM1 0x1B000 0x0025000 {
1919
.ANY (+RO)
2020
}
2121
RW_IRAM0 0x20002ef8 UNINIT 0x000000c0 { ;no init section
22-
*(noinit)
22+
*(*noinit)
2323
}
2424
RW_IRAM1 0x20002FB8 0x00005048 {
2525
.ANY (+RW +ZI)

‎targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ LR_IROM1 0x18000 0x0028000 {
1919
.ANY (+RO)
2020
}
2121
RW_IRAM0 0x20002000 UNINIT 0x000000c0 { ;no init section
22-
*(noinit)
22+
*(*noinit)
2323
}
2424
RW_IRAM1 0x200020C0 0x00001F40 {
2525
.ANY (+RW +ZI)

‎targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ LR_IROM1 0x0001B000 0x0025000 {
1919
.ANY (+RO)
2020
}
2121
RW_IRAM0 0x20002ef8 UNINIT 0x000000c0 { ;no init section
22-
*(noinit)
22+
*(*noinit)
2323
}
2424
RW_IRAM1 0x20002FB8 0x00001048 {
2525
.ANY (+RW +ZI)

‎targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/nRF52832.sct‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ LR_IROM1 0x1C000 0x0064000 {
1919
.ANY (+RO)
2020
}
2121
RW_IRAM0 0x20002EF8 UNINIT 0x000000D8 { ;no init section
22-
*(noinit)
22+
*(*noinit)
2323
}
2424
RW_IRAM1 0x20002FD0 0x0000D030 {
2525
.ANY (+RW +ZI)

‎targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52832.sct‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ LR_IROM1 0x21000 0x00DF000 {
55
.ANY (+RO)
66
}
77
RW_IRAM0 0x20003288 UNINIT 0x000000F8 { ;no init section
8-
*(noinit)
8+
*(*noinit)
99
}
1010
RW_IRAM1 0x20003380 0x0003cc80 {
1111
.ANY (+RW +ZI)

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