Update to QPDS 24.3.1 tools release

This is a significant update to all hardware and software objects within
this repo as they are all updated to build under the QPDS 24.3.1 tools
environment.

The Quartus 24.3.1 build 102 tools release contains a defect that is
resolved by applying patch 1.14. This is required by this release in
order to properly build the hardware examples.

Some of the more notable changes are listed below:

Agilex 5 SoC component is upgraded to version 6.0.0

HPS EMIF component is upgraded to version 2.0.0

Configuration Clock component is upgraded to version 19.1.5

Reset Release IP component is upgraded to version 1.0.1

u-boot-socfpga, arm-trusted-firmware and linux-socfpga are updated to
the latest tag, QPDS24.3.1_REL_GSRD_PR

toybox is updated to the latest tag, 0.8.12

Disabled all advanced calibration options for the HPS EMIF controller in
all of the designs. This shortens the boot time consumed by EMIF
calibration.

Added the clusterpwrstat_el1 to the cache_regs.c application which
displays how much L3 cache is enabled in the cluster.

In the 24.3.1 tools, the aXmmusecsid value was changed from 1'b0 to 1'b1
and this prevents cache coherent transactions from interacting with the
cache subsystem properly when they pass through the F2H bridge. We have
implemented a script that sets that value back to 1'b0 and allows the
cache coherent demo to operate properly again.

Signed-off-by: Rod Frazer <rod.frazer@altera.com>

Author: rodfrazer-intel

README.md

@@ -1,12 +1,13 @@
 # agilex5-demo-hps2fpga-interfaces
 <!-- SPDX-FileCopyrightText: Copyright (C) 2024 Intel Corporation -->
+<!-- SPDX-FileCopyrightText: Copyright (C) 2025 Altera Corporation -->
 <!-- SPDX-License-Identifier: MIT-0 -->
 
 - **id**:
 - **title**: agilex5-demo-hps2fpga-interfaces
 - **source**: GitHub
 - **family**: Agilex 5
-- **quartus_version**: Version 24.3.0 Build 212 11/18/2024 SC Pro Edition
+- **quartus_version**: Version 24.3.1 Build 102 01/14/2025 Patches 1.14 SC Pro Edition
 - **devkit**: Agilex 5 FPGA E-Series 065B Premium Development Kit, and others
 - **device_part**: A5ED065BB32AE5SR0, A5ED065BB32AE4SR0, A5ED065BB32AE6SR0
 - **description**: Agilex 5 HPS-to-FPGA interfaces demos.
@@ -26,7 +27,7 @@ The project build instructions are documented [**here**](./documentation/17_buil
 
 | Repo Directory | Board Info |
 | :--- | :--- |
-| brd_altera_a5e065_premium_es | **Company:** Altera, An Intel Company<br>**Board Name:** Agilex* 5 FPGA E-Series 065B Premium Development Kit<br>**OPN:** DK-A5E065BB32AES1<br>**Comment:** ES device |
+| brd_altera_a5e065_premium_es | **Company:** Altera Corporation<br>**Board Name:** Agilex* 5 FPGA E-Series 065B Premium Development Kit<br>**OPN:** DK-A5E065BB32AES1<br>**Comment:** ES device |
 | brd_arrow_axe5_eagle_es | **Company:** Arrow Electronics, Inc.<br>**Board Name:** Arrow AXE5-Eagle Development Platform<br>**OPN:** AXE5-EAGLE-ES<br>**Comment:** ES device |
 | brd_criticallink_mitysbc_es | **Company:** Critical Link, LLC<br>**Board Name:** MitySBC-A5E Single Board Computer<br>**OPN:** A5ED-B9-C7F-RC-SBC-X<br>**Comment:** ES device |
 | brd_macnica_sulfur_es_125 | **Company:** Macnica, Inc.<br>**Board Name:** Macnica Mpression Sulfur Kit / Type A<br>**OPN:** ALTSULFUR_A5ED065B_E5_ES0_typeA<br>**Comment:** ES device - 125MHz SDM_OSC_CLK |

SECURITY.md

@@ -1,6 +1,5 @@
-# Security Policy
-Intel is committed to rapidly addressing security vulnerabilities affecting our customers and providing clear guidance on the solution, impact, severity and mitigation. 
-
-## Reporting a Vulnerability
-Please report any security vulnerabilities in this project [utilizing the guidelines here](https://www.intel.com/content/www/us/en/security-center/vulnerability-handling-guidelines.html).
-
+# Security Policy
+Altera is committed to the security of its products.
+
+## Reporting a Vulnerability
+Security vulnerabilities in this project can be reported to Altera’s security incident response team utilizing the guidelines here: https://www.altera.com/security/psirt.html.

brd_altera_a5e065_premium_es/hw_base/a55_do_create_no_pins_hps.tcl

@@ -1,10 +1,11 @@
 #!/bin/bash
 #
 # SPDX-FileCopyrightText: Copyright (C) 2024 Intel Corporation
+# SPDX-FileCopyrightText: Copyright (C) 2025 Altera Corporation
 # SPDX-License-Identifier: MIT-0
 #
 
-TAG_NAME="QPDS24.3_REL_GSRD_PR"
+TAG_NAME="QPDS24.3.1_REL_GSRD_PR"
 
 # change into the directory of this script
 cd $(dirname ${0})
@@ -81,6 +82,7 @@ ln -s ../arm-trusted-firmware/build/agilex5/release/bl31.bin \
 	|| { echo "ERROR" ; exit 1 ; }
 
 PATCH_FILES="
+../../../common_sw/u-boot_patches/scripts_dtc_pylibfdt_libfdt.i_shipped.patch \
 ../../../common_sw/u-boot_patches/include-exports.h.patch \
 ../../../common_sw/u-boot_patches/include-configs-socfpga_soc64_common.h.patch \
 ../../../common_sw/u-boot_patches/include-_exports.h.patch \

brd_altera_a5e065_premium_es/hw_base/a76_do_create_no_pins_hps.tcl

@@ -1,10 +1,11 @@
 #!/bin/bash
 #
 # SPDX-FileCopyrightText: Copyright (C) 2024 Intel Corporation
+# SPDX-FileCopyrightText: Copyright (C) 2025 Altera Corporation
 # SPDX-License-Identifier: MIT-0
 #
 
-TAG_NAME="QPDS24.3_REL_GSRD_PR"
+TAG_NAME="QPDS24.3.1_REL_GSRD_PR"
 
 # change into the directory of this script
 cd $(dirname ${0})

brd_altera_a5e065_premium_es/sw_builds/build_bootloaders.sh

@@ -1,10 +1,11 @@
 #!/bin/bash
 #
 # SPDX-FileCopyrightText: Copyright (C) 2024 Intel Corporation
+# SPDX-FileCopyrightText: Copyright (C) 2025 Altera Corporation
 # SPDX-License-Identifier: MIT-0
 #
 
-TAG_NAME="0.8.11"
+TAG_NAME="0.8.12"
 
 # change into the directory of this script
 cd $(dirname ${0})

brd_altera_a5e065_premium_es/sw_builds/build_linux_kernel.sh

@@ -1,10 +1,11 @@
 #!/bin/bash
 #
 # SPDX-FileCopyrightText: Copyright (C) 2024 Intel Corporation
+# SPDX-FileCopyrightText: Copyright (C) 2025 Altera Corporation
 # SPDX-License-Identifier: MIT-0
 #
 
-TAG_NAME="QPDS24.3_REL_GSRD_PR"
+TAG_NAME="QPDS24.3.1_REL_GSRD_PR"
 
 # change into the directory of this script
 cd $(dirname ${0})
@@ -81,6 +82,7 @@ ln -s ../arm-trusted-firmware/build/agilex5/release/bl31.bin \
 	|| { echo "ERROR" ; exit 1 ; }
 
 PATCH_FILES="
+../../../common_sw/u-boot_patches/scripts_dtc_pylibfdt_libfdt.i_shipped.patch \
 ../../../common_sw/u-boot_patches/include-exports.h.patch \
 ../../../common_sw/u-boot_patches/include-configs-socfpga_soc64_common.h.patch \
 ../../../common_sw/u-boot_patches/include-_exports.h.patch \