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Update to QPDS 24.3 tools release
This is a significant update to all hardware and software objects within this repo as they are all updated to build under the QPDS 24.3 tools environment. Some of the more notable changes are listed below: The HPS and HPS EMIF cores are completely incompatible in the 24.3 tools, so all hardware designs had to remove and re-instantiate both cores. The 24.3 tools do not offer any auto upgrade option for these two cores. The updated HPS EMIF core no longer supports the QPRS preset format from previous tool releases. All QPRS files have been removed from the repo. The HPS EMIF configuration is captured in the system TCL definition alone. The no_pins_hps PD subsystems for each board were completely reimplemented with the new HPS and HPS EMIF cores. All the top-level projects were reimplemented with the new no_pins_hps instance. All demos with HPS/FPGA memory mapped bridges enabled have been modified to set the default interconnect latency to 4. This was done to address timing closure issues that would otherwise be present. As the devices are still ES and the tooling is still maturing towards PRQ, I am not trying to implement any final resolutions to timing closure in an optimized fashion. Implemented an SDC file for the JTAG interface in the hw_hps_jamb demo. The no_pins_top.v files were all updated with slight changes to the name used in the EMIF signals. The bootloader and linux kernel build scripts were updated to fetch the QPDS 24.3 tag points out of their respective repos. Signed-off-by: Rod Frazer <rod.frazer@intel.com>
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brd_altera_a5e065_premium_es/hw_base/DDR4-1600L_800MHz_CL12_alloff_component_1CS_DDP_32Gb_2Gx16.qprs

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