hdl.dsl: bring new naming rules to FSM

Author: tpwrules

amaranth/hdl/_dsl.py

@@ -5,7 +5,7 @@
 import warnings
 import sys
 
-from .._utils import flatten
+from .._utils import flatten, validate_name
 from ..utils import bits_for
 from .. import tracer
 from ._ast import *
@@ -164,6 +164,7 @@ def __init__(self, data):
         self.decoding = data["decoding"]
 
     def ongoing(self, name):
+        validate_name(name, "FSM state")
         if name not in self.encoding:
             self.encoding[name] = len(self.encoding)
             fsm_name = self._data["name"]
@@ -426,6 +427,9 @@ def FSM(self, init=None, domain="sync", name="fsm", *, reset=None):
             warnings.warn("`reset=` is deprecated, use `init=` instead",
                           DeprecationWarning, stacklevel=2)
             init = reset
+        validate_name(name, "FSM name")
+        validate_name(init, "FSM state", none_ok=True)
+        validate_name(domain, "FSM clock domain")
         fsm_data = self._set_ctrl("FSM", {
             "name":     name,
             "init":     init,
@@ -455,6 +459,7 @@ def FSM(self, init=None, domain="sync", name="fsm", *, reset=None):
     @contextmanager
     def State(self, name):
         self._check_context("FSM State", context="FSM")
+        validate_name(name, "FSM state")
         src_loc = tracer.get_src_loc(src_loc_at=1)
         fsm_data = self._get_ctrl("FSM")
         if name in fsm_data["states"]:
@@ -481,6 +486,7 @@ def next(self):
     @next.setter
     def next(self, name):
         if self._ctrl_context != "FSM":
+            validate_name(name, "FSM state")
             for level, (ctrl_name, ctrl_data) in enumerate(reversed(self._ctrl_stack)):
                 if ctrl_name == "FSM":
                     if name not in ctrl_data["encoding"]:

tests/test_hdl_dsl.py

@@ -793,6 +793,37 @@ def test_FSM_wrong_next(self):
             with m.FSM():
                 m.next = "FOO"
 
+    def test_FSM_wrong_name(self):
+        m = Module()
+        with self.assertRaisesRegex(TypeError,
+                r"^FSM name must be a string, not 1$"):
+            with m.FSM(name=1):
+                pass
+        with self.assertRaisesRegex(TypeError,
+                r"^FSM state must be a string, not 1$"):
+            with m.FSM(init=1):
+                pass
+        with self.assertRaisesRegex(TypeError,
+                r"^FSM clock domain must be a string, not 1$"):
+            with m.FSM(domain=1):
+                pass
+        with self.assertRaisesRegex(TypeError,
+                r"^FSM state must be a string, not 1$"):
+            with m.FSM():
+                with m.State(1):
+                    pass
+        with self.assertRaisesRegex(TypeError,
+                r"^FSM state must be a string, not 1$"):
+            with m.FSM():
+                with m.State("FOO"):
+                    m.next = 1
+        with self.assertRaisesRegex(TypeError,
+                r"^FSM state must be a string, not 1$"):
+            with m.FSM() as fsm:
+                s = fsm.ongoing(1)
+                with m.State("FOO"):
+                    m.next = "FOO"
+
     def test_If_inside_FSM_wrong(self):
         m = Module()
         with m.FSM():