hdl.dsl: bring new naming rules to FSM

States are not "names" as such and still allowed to be (relatively)
arbitrary objects.

Author: tpwrules

amaranth/hdl/_dsl.py

@@ -5,7 +5,7 @@
 import warnings
 import sys
 
-from .._utils import flatten
+from .._utils import flatten, validate_name
 from ..utils import bits_for
 from .. import tracer
 from ._ast import *
@@ -426,6 +426,8 @@ def FSM(self, init=None, domain="sync", name="fsm", *, reset=None):
             warnings.warn("`reset=` is deprecated, use `init=` instead",
                           DeprecationWarning, stacklevel=2)
             init = reset
+        validate_name(name, "FSM name")
+        validate_name(domain, "FSM clock domain")
         fsm_data = self._set_ctrl("FSM", {
             "name":     name,
             "init":     init,

tests/test_hdl_dsl.py

@@ -792,6 +792,17 @@ def test_FSM_wrong_next(self):
             with m.FSM():
                 m.next = "FOO"
 
+    def test_FSM_wrong_name(self):
+        m = Module()
+        with self.assertRaisesRegex(TypeError,
+                r"^FSM name must be a string, not 1$"):
+            with m.FSM(name=1):
+                pass
+        with self.assertRaisesRegex(TypeError,
+                r"^FSM clock domain must be a string, not 1$"):
+            with m.FSM(domain=1):
+                pass
+
     def test_If_inside_FSM_wrong(self):
         m = Module()
         with m.FSM():