docs/user_guide: Update axi adc regmap info

Signed-off-by: Stanca Pop <stanca.pop@analog.com>

Author: StancaPop

docs/user_guide/ip_cores/axi_adc/index.rst

@@ -218,50 +218,59 @@ see :ref:`axi_adc adc-channel` section.
    To find the instantiation of this module search for ``up_adc_channel`` inside
    the IP's directory.
 
+.. _generic-adc-register-access:
+
 Register access
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 The ADC IP supports **16 channels**, numbered from **0 to 15**. The **base
 registers** start at offset ``0x0`` and the **common (global) registers** start
-at offset ``0x10``. Each **channel** has its own register block, starting from
-offset ``0x100`` (for channel 0). Each subsequent channel is spaced by ``0x10``
-(HDL addressing) or ``0x40`` (WORD aligned).
+at address ``0x10``. Each **channel** has its own register block, starting from
+address ``0x100`` (for channel 0). Each subsequent channel is spaced by ``0x10``
+(HDL register address) or ``0x40`` (Software addressing).
 
 Let's say the ADC IP base address is 0x44A0_0000. Here is how the channel offset
 is computed: 
 
 .. math::
 
-   \text{Address}_{HDL} = 0x44A0\_0000 + 0x100 + (n \times 0x10) \\
-   \text{Address}_{WORD} = 0x44A0\_0000 + 0x400 + (n \times 0x40)
+   \text{HDL}_{reg} = 0x100 + (n \times 0x10) \\
+
+.. math::   
+
+   \text{Software}_{addr} = IP_BaseAddr + (\text{HDL}_{reg} << 2) = 0x44A0\_0000 + 0x400 + (n \times 0x40)
 
 This means the first register's address ( **``CHAN_CNTRL``**) is:
 
 - For **channel 0**:
-  - ``0x44A0_0100`` (HDL addressing)
-  - ``0x44A0_0400`` (WORD aligned addressing)
+
+  - ``0x0100`` (HDL register)=> ``0x44A0_0400`` (Software addressing)
+
 - For **channel 3**:
-  - ``0x44A0_0140`` (HDL addressing)
-  - ``0x44A0_0500`` (WORD aligned addressing)
+
+  - ``0x0130`` (HDL register) => ``0x44A0_04C0`` (Software addressing)
 - For **channel 15**:
-  - ``0x44A0_01F0`` (HDL addressing)
-  - ``0x44A0_07C0`` (WORD aligned addressing)
+
+  - ``0x01F0`` (HDL register) => ``0x44A0_07C0`` (Software addressing)
 
 If you want to access the **``CHAN_CNTRL_3``** register, its address is:
 
 - For **channel 0**:
-  - ``0x44A6_0106`` (HDL addressing)
-  - ``0x44A6_0418`` (WORD aligned addressing)
+
+  - ``0x0106`` (HDL register) => ``0x44A6_0418`` (Software addressing)
+
 - For **channel 5**:
-  - ``0x44A6_0156`` (HDL addressing)
-  - ``0x44A6_0558`` (WORD aligned addressing)
 
+  - ``0x0156`` (HDL register) => ``0x44A6_0558`` (Software addressing)
 In general, the address for the ``CHAN_CNTRL_3`` register of **channel *n*** can be calculated as:
 
 .. math::
+  
+   \text{HDL}_{reg} = 0x100 + (n \times 0x10) + 0x06 \\
 
-   \text{Address}_{HDL} = 0x44A6\_0000 + 0x100 + (n \times 0x10) + 0x06 \\
-   \text{Address}_{WORD}  = 0x44A6\_0000 + 0x400 + (n \times 0x40) + 0x18
+.. math::
+  
+   \text{Software}_{addr}  = IP_base_addr + 0x400 + (n \times 0x40) + 0x18
 
 Typical Register Map base addresses
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~