Skip to content

Commit 8df3511

Browse files
ericlewisericlewis
committed
feat(board): add Satellite 1 CORE (rev 5.1)
1 parent 15e71a6 commit 8df3511

File tree

2 files changed

+214
-0
lines changed

2 files changed

+214
-0
lines changed

‎boards.txt‎

Lines changed: 154 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49849,3 +49849,157 @@ cyobot_v2_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
4984949849
cyobot_v2_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
4985049850

4985149851
##############################################################
49852+
49853+
# Satellite 1 CORE (rev 5.1)
49854+
49855+
sat1core_rev5_1.name=Satellite 1 CORE (rev 5.1)
49856+
49857+
sat1core_rev5_1.bootloader.tool=esptool_py
49858+
sat1core_rev5_1.bootloader.tool.default=esptool_py
49859+
49860+
sat1core_rev5_1.upload.tool=esptool_py
49861+
sat1core_rev5_1.upload.tool.default=esptool_py
49862+
sat1core_rev5_1.upload.tool.network=esp_ota
49863+
49864+
sat1core_rev5_1.upload.maximum_size=1310720
49865+
sat1core_rev5_1.upload.maximum_data_size=327680
49866+
sat1core_rev5_1.upload.flags=
49867+
sat1core_rev5_1.upload.extra_flags=
49868+
sat1core_rev5_1.upload.use_1200bps_touch=false
49869+
sat1core_rev5_1.upload.wait_for_upload_port=false
49870+
49871+
sat1core_rev5_1.serial.disableDTR=false
49872+
sat1core_rev5_1.serial.disableRTS=false
49873+
49874+
sat1core_rev5_1.build.tarch=xtensa
49875+
sat1core_rev5_1.build.bootloader_addr=0x0
49876+
sat1core_rev5_1.build.target=esp32s3
49877+
sat1core_rev5_1.build.mcu=esp32s3
49878+
sat1core_rev5_1.build.core=esp32
49879+
sat1core_rev5_1.build.variant=satellite1_core_rev5_1
49880+
sat1core_rev5_1.build.board=SATELLITE1_CORE_REV5_1
49881+
49882+
sat1core_rev5_1.build.usb_mode=1
49883+
sat1core_rev5_1.build.cdc_on_boot=1
49884+
sat1core_rev5_1.build.msc_on_boot=0
49885+
sat1core_rev5_1.build.dfu_on_boot=0
49886+
sat1core_rev5_1.build.f_cpu=240000000L
49887+
sat1core_rev5_1.build.flash_size=16MB (128Mb)
49888+
sat1core_rev5_1.build.flash_freq=80m
49889+
sat1core_rev5_1.build.flash_mode=dio
49890+
sat1core_rev5_1.build.boot=qio
49891+
sat1core_rev5_1.build.boot_freq=80m
49892+
sat1core_rev5_1.build.partitions=default
49893+
sat1core_rev5_1.build.defines=-DBOARD_HAS_PSRAM
49894+
sat1core_rev5_1.build.loop_core=
49895+
sat1core_rev5_1.build.event_core=
49896+
sat1core_rev5_1.build.psram_type=opi
49897+
sat1core_rev5_1.build.memory_type={build.boot}_{build.psram_type}
49898+
49899+
sat1core_rev5_1.menu.PSRAM.opi=Enabled
49900+
sat1core_rev5_1.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
49901+
sat1core_rev5_1.menu.PSRAM.opi.build.psram_type=opi
49902+
49903+
sat1core_rev5_1.menu.FlashMode.qio=QIO 80MHz
49904+
sat1core_rev5_1.menu.FlashMode.qio.build.flash_mode=dio
49905+
sat1core_rev5_1.menu.FlashMode.qio.build.boot=qio
49906+
sat1core_rev5_1.menu.FlashMode.qio.build.boot_freq=80m
49907+
sat1core_rev5_1.menu.FlashMode.qio.build.flash_freq=80m
49908+
49909+
sat1core_rev5_1.menu.FlashSize.16M=16MB (128Mb)
49910+
sat1core_rev5_1.menu.FlashSize.16M.build.flash_size=16MB
49911+
49912+
sat1core_rev5_1.menu.LoopCore.1=Core 1
49913+
sat1core_rev5_1.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
49914+
sat1core_rev5_1.menu.LoopCore.0=Core 0
49915+
sat1core_rev5_1.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
49916+
49917+
sat1core_rev5_1.menu.EventsCore.1=Core 1
49918+
sat1core_rev5_1.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
49919+
sat1core_rev5_1.menu.EventsCore.0=Core 0
49920+
sat1core_rev5_1.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
49921+
49922+
sat1core_rev5_1.menu.USBMode.default=Hardware CDC and JTAG
49923+
sat1core_rev5_1.menu.USBMode.default.build.usb_mode=1
49924+
sat1core_rev5_1.menu.USBMode.hwcdc=USB-OTG (TinyUSB)
49925+
sat1core_rev5_1.menu.USBMode.hwcdc.build.usb_mode=0
49926+
49927+
sat1core_rev5_1.menu.CDCOnBoot.cdc=Enabled
49928+
sat1core_rev5_1.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
49929+
sat1core_rev5_1.menu.CDCOnBoot.default=Disabled
49930+
sat1core_rev5_1.menu.CDCOnBoot.default.build.cdc_on_boot=0
49931+
49932+
sat1core_rev5_1.menu.MSCOnBoot.default=Disabled
49933+
sat1core_rev5_1.menu.MSCOnBoot.default.build.msc_on_boot=0
49934+
sat1core_rev5_1.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
49935+
sat1core_rev5_1.menu.MSCOnBoot.msc.build.msc_on_boot=1
49936+
49937+
sat1core_rev5_1.menu.DFUOnBoot.default=Disabled
49938+
sat1core_rev5_1.menu.DFUOnBoot.default.build.dfu_on_boot=0
49939+
sat1core_rev5_1.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
49940+
sat1core_rev5_1.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
49941+
49942+
sat1core_rev5_1.menu.UploadMode.default=UART0 / Hardware CDC
49943+
sat1core_rev5_1.menu.UploadMode.default.upload.use_1200bps_touch=false
49944+
sat1core_rev5_1.menu.UploadMode.default.upload.wait_for_upload_port=false
49945+
sat1core_rev5_1.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
49946+
sat1core_rev5_1.menu.UploadMode.cdc.upload.use_1200bps_touch=true
49947+
sat1core_rev5_1.menu.UploadMode.cdc.upload.wait_for_upload_port=true
49948+
49949+
sat1core_rev5_1.menu.PartitionScheme.gen4esp32scheme1=Small App w/ OTA + Huge FS (2MB APP/2MB OTA/12MB SPIFFS)
49950+
sat1core_rev5_1.menu.PartitionScheme.gen4esp32scheme1.build.custom_partitions=gen4esp32_2MBapp_2MBota_12MBspiffs
49951+
sat1core_rev5_1.menu.PartitionScheme.gen4esp32scheme1.upload.maximum_size=2097152
49952+
sat1core_rev5_1.menu.PartitionScheme.gen4esp32scheme2=Medium App w/ OTA + Large FS (4MB APP/4MB OTA/7MB SPIFFS)
49953+
sat1core_rev5_1.menu.PartitionScheme.gen4esp32scheme2.build.custom_partitions=gen4esp32_4MBapp_4MBota_7MBspiffs
49954+
sat1core_rev5_1.menu.PartitionScheme.gen4esp32scheme2.upload.maximum_size=4718592
49955+
sat1core_rev5_1.menu.PartitionScheme.gen4esp32scheme3=Large App w/ OTA (8MB APP/8MB OTA)
49956+
sat1core_rev5_1.menu.PartitionScheme.gen4esp32scheme3.build.custom_partitions=gen4esp32_8MBapp_8MBota
49957+
sat1core_rev5_1.menu.PartitionScheme.gen4esp32scheme3.upload.maximum_size=8323072
49958+
49959+
sat1core_rev5_1.menu.CPUFreq.240=240MHz (WiFi)
49960+
sat1core_rev5_1.menu.CPUFreq.240.build.f_cpu=240000000L
49961+
sat1core_rev5_1.menu.CPUFreq.160=160MHz (WiFi)
49962+
sat1core_rev5_1.menu.CPUFreq.160.build.f_cpu=160000000L
49963+
sat1core_rev5_1.menu.CPUFreq.80=80MHz (WiFi)
49964+
sat1core_rev5_1.menu.CPUFreq.80.build.f_cpu=80000000L
49965+
sat1core_rev5_1.menu.CPUFreq.40=40MHz
49966+
sat1core_rev5_1.menu.CPUFreq.40.build.f_cpu=40000000L
49967+
sat1core_rev5_1.menu.CPUFreq.20=20MHz
49968+
sat1core_rev5_1.menu.CPUFreq.20.build.f_cpu=20000000L
49969+
sat1core_rev5_1.menu.CPUFreq.10=10MHz
49970+
sat1core_rev5_1.menu.CPUFreq.10.build.f_cpu=10000000L
49971+
49972+
sat1core_rev5_1.menu.UploadSpeed.921600=921600
49973+
sat1core_rev5_1.menu.UploadSpeed.921600.upload.speed=921600
49974+
sat1core_rev5_1.menu.UploadSpeed.115200=115200
49975+
sat1core_rev5_1.menu.UploadSpeed.115200.upload.speed=115200
49976+
sat1core_rev5_1.menu.UploadSpeed.256000.windows=256000
49977+
sat1core_rev5_1.menu.UploadSpeed.256000.upload.speed=256000
49978+
sat1core_rev5_1.menu.UploadSpeed.230400.windows.upload.speed=256000
49979+
sat1core_rev5_1.menu.UploadSpeed.230400=230400
49980+
sat1core_rev5_1.menu.UploadSpeed.230400.upload.speed=230400
49981+
sat1core_rev5_1.menu.UploadSpeed.460800.linux=460800
49982+
sat1core_rev5_1.menu.UploadSpeed.460800.macosx=460800
49983+
sat1core_rev5_1.menu.UploadSpeed.460800.upload.speed=460800
49984+
sat1core_rev5_1.menu.UploadSpeed.512000.windows=512000
49985+
sat1core_rev5_1.menu.UploadSpeed.512000.upload.speed=512000
49986+
49987+
sat1core_rev5_1.menu.DebugLevel.none=None
49988+
sat1core_rev5_1.menu.DebugLevel.none.build.code_debug=0
49989+
sat1core_rev5_1.menu.DebugLevel.error=Error
49990+
sat1core_rev5_1.menu.DebugLevel.error.build.code_debug=1
49991+
sat1core_rev5_1.menu.DebugLevel.warn=Warn
49992+
sat1core_rev5_1.menu.DebugLevel.warn.build.code_debug=2
49993+
sat1core_rev5_1.menu.DebugLevel.info=Info
49994+
sat1core_rev5_1.menu.DebugLevel.info.build.code_debug=3
49995+
sat1core_rev5_1.menu.DebugLevel.debug=Debug
49996+
sat1core_rev5_1.menu.DebugLevel.debug.build.code_debug=4
49997+
sat1core_rev5_1.menu.DebugLevel.verbose=Verbose
49998+
sat1core_rev5_1.menu.DebugLevel.verbose.build.code_debug=5
49999+
50000+
sat1core_rev5_1.menu.EraseFlash.none=Disabled
50001+
sat1core_rev5_1.menu.EraseFlash.none.upload.erase_cmd=
50002+
sat1core_rev5_1.menu.EraseFlash.all=Enabled
50003+
sat1core_rev5_1.menu.EraseFlash.all.upload.erase_cmd=-e
50004+
50005+
##############################################################

‎variants/satellite1_core_rev5_1/pins_arduino.h‎

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
1+
/* Satellite 1 CORE ‒ rev 5.1 (R2025-03-18)
2+
* ESP32-S3-WROOM-1-N16R8 · 16 MB Octal-SPI flash + 8 MB Octal-SPI PSRAM
3+
* 40-pin header is a one-for-one Raspberry-Pi-Zero footprint (BCM numbering).
4+
*/
5+
#ifndef Pins_Arduino_h
6+
#define Pins_Arduino_h
7+
8+
#include <stdint.h>
9+
#include "soc/soc_caps.h"
10+
11+
/* ───────── USB descriptors (used only when USB-Mode = TinyUSB) ───────── */
12+
#define USB_VID 0x303A // Espressif Systems
13+
#define USB_PID 0x80F2 // provisional, unused PID
14+
#define USB_MANUFACTURER "FutureProofHomes"
15+
#define USB_PRODUCT "Satellite1 CORE rev5.1"
16+
17+
/* ───────── Pi-header aliases (primary UART / I²C / I²S) ─────────────── */
18+
static const uint8_t TX = 17; // BCM14 (header pin 8)
19+
static const uint8_t RX = 16; // BCM15 (header pin 10)
20+
21+
static const uint8_t SDA = 38; // BCM2 (pin 3)
22+
static const uint8_t SCL = 39; // BCM3 (pin 5)
23+
24+
/* Wire0 definition expected by core */
25+
#define PIN_WIRE_SDA SDA
26+
#define PIN_WIRE_SCL SCL
27+
#define SDA2 SDA // back-compat
28+
#define SCL2 SCL
29+
30+
/* I²S */
31+
static const uint8_t I2S_BCLK = 36; // BCM18 (pin 12)
32+
static const uint8_t I2S_LRCLK = 37; // BCM19 (pin 35)
33+
static const uint8_t I2S_DIN = 35; // BCM20 (pin 38) ← ADC
34+
static const uint8_t I2S_DOUT = 34; // BCM21 (pin 40) → DAC
35+
36+
/* Optional default SPI (remappable via GPIO-matrix) */
37+
static const uint8_t SS = 5; // BCM8 (CE0)
38+
static const uint8_t MOSI = 23; // BCM10
39+
static const uint8_t MISO = 22; // BCM9
40+
static const uint8_t SCK = 18; // BCM11
41+
42+
/* ───────── On-board user interface ───────── */
43+
#define LED_BUILTIN 45 // red status LED (active-HIGH)
44+
#define BUILTIN_LED LED_BUILTIN
45+
46+
#define BUTTON_BUILTIN 0 // SW2, active-LOW
47+
48+
/* ───────── PSRAM / flash configuration ───────── */
49+
#define BOARD_HAS_PSRAM 1
50+
#define DEFAULT_PSRAM_OCT 1 // 8-bit OPI @ 120 MHz
51+
52+
/* ───────── ADC & touch aliases ───────── */
53+
static const uint8_t A0 = 1; static const uint8_t T4 = 4;
54+
static const uint8_t A1 = 2; static const uint8_t T5 = 5;
55+
static const uint8_t A2 = 3; static const uint8_t T6 = 6;
56+
static const uint8_t A3 = 4; static const uint8_t T7 = 7;
57+
static const uint8_t A4 = 6; static const uint8_t T8 = 8;
58+
static const uint8_t A5 = 7;
59+
60+
#endif /* Pins_Arduino_h */

0 commit comments

Comments
 (0)