Apply pre-commit suggested changes (formating)

Author: Quentin Berthet

hls4ml/backends/vitis_accelerator/supported_boards.json

@@ -23,4 +23,4 @@
       "platform": "xilinx_vck5000_gen4x8_qdma_2_202220_1",
       "memory":{"type": "ddr", "channels": 3, "capacity": 12}
     }
-  }
+  }

hls4ml/backends/vitis_accelerator/vitis_accelerator_backend.py

@@ -1,6 +1,7 @@
 import os
-import sys
 import subprocess
+import sys
+
 import numpy as np
 
 from hls4ml.backends import VitisBackend, VivadoBackend
@@ -23,7 +24,7 @@ def create_initial_config(
         num_thread=1,
         batchsize=8192,
         hw_quant=False,
-        vivado_directives=[],
+        vivado_directives=None,
     ):
         """
         Create initial accelerator config with default parameters
@@ -64,15 +65,18 @@ def build(
         if "linux" in sys.platform:
             if "XILINX_VITIS" not in os.environ:
                 raise Exception(
-                    "XILINX_VITIS environmental variable missing. Please install XRT and Vitis, and run the setup scripts before building"
+                    "XILINX_VITIS environmental variable missing."
+                    " Please install XRT and Vitis, and run the setup scripts before building"
                 )
             if "XILINX_XRT" not in os.environ:
                 raise Exception(
-                    "XILINX_XRT environmental variable missing. Please install XRT and Vitis, and run the setup scripts before building"
+                    "XILINX_XRT environmental variable missing."
+                    " Please install XRT and Vitis, and run the setup scripts before building"
                 )
             if "XILINX_VIVADO" not in os.environ:
                 raise Exception(
-                    "XILINX_VIVADO environmental variable missing. Please install XRT and Vitis, and run the setup scripts before building"
+                    "XILINX_VIVADO environmental variable missing."
+                    " Please install XRT and Vitis, and run the setup scripts before building"
                 )
 
             curr_dir = os.getcwd()
@@ -106,14 +110,10 @@ def build(
             command = "make " + target
 
             # Pre-loading libudev
-            ldconfig_output = subprocess.check_output(["ldconfig", "-p"]).decode(
-                "utf-8"
-            )
+            ldconfig_output = subprocess.check_output(["ldconfig", "-p"]).decode("utf-8")
             for line in ldconfig_output.split("\n"):
                 if "libudev.so" in line and "x86" in line:
-                    command = (
-                        "LD_PRELOAD=" + line.split("=>")[1].strip() + " " + command
-                    )
+                    command = "LD_PRELOAD=" + line.split("=>")[1].strip() + " " + command
                     break
             os.system(command)
 
@@ -129,9 +129,7 @@ def numpy_to_dat(self, model, x):
         expected_shape = model.get_input_variables()[0].size()
         actual_shape = np.prod(x.shape[1:])
         if expected_shape != actual_shape:
-            raise Exception(
-                f"Input shape mismatch, got {x.shape}, expected (_, {expected_shape})"
-            )
+            raise Exception(f"Input shape mismatch, got {x.shape}, expected (_, {expected_shape})")
 
         # Write to tb_data/tb_input_features.dat
         samples = x.reshape(x.shape[0], -1)
@@ -175,18 +173,10 @@ def _register_flows(self):
         )
 
         writer_passes = ["make_stamp", "vitisaccelerator:write_hls"]
-        self._writer_flow = register_flow(
-            "write", writer_passes, requires=["vitis:ip"], backend=self.name
-        )
+        self._writer_flow = register_flow("write", writer_passes, requires=["vitis:ip"], backend=self.name)
 
         ip_flow_requirements = get_flow("vivado:ip").requires.copy()
-        ip_flow_requirements.insert(
-            ip_flow_requirements.index("vivado:init_layers"), validation_flow
-        )
-        ip_flow_requirements.insert(
-            ip_flow_requirements.index("vivado:apply_templates"), template_flow
-        )
+        ip_flow_requirements.insert(ip_flow_requirements.index("vivado:init_layers"), validation_flow)
+        ip_flow_requirements.insert(ip_flow_requirements.index("vivado:apply_templates"), template_flow)
 
-        self._default_flow = register_flow(
-            "ip", None, requires=ip_flow_requirements, backend=self.name
-        )
+        self._default_flow = register_flow("ip", None, requires=ip_flow_requirements, backend=self.name)

hls4ml/backends/vitis_accelerator/vitis_accelerator_config.py

@@ -11,9 +11,7 @@ def __init__(self, config):
             raise Exception("Missing AcceleratorConfig")
 
         self.board = accel_config.get("Board", "alveo-u55c")
-        self.supported_boards = json.load(
-            open(os.path.dirname(__file__) + "/supported_boards.json")
-        )
+        self.supported_boards = json.load(open(os.path.dirname(__file__) + "/supported_boards.json"))
         if self.board in self.supported_boards.keys():
             board_info = self.supported_boards[self.board]
             self.board_type = board_info["board_type"]

hls4ml/backends/vitis_accelerator/vivado_directives.json

@@ -131,7 +131,7 @@
                         }
                     }
                 }
-            } 
+            }
         }
-    } 
-}
+    }
+}

hls4ml/templates/vitis_accelerator/hls_config.tcl

@@ -1,2 +1,2 @@
 config_interface -m_axi_auto_max_ports=true
-config_interface -m_axi_offset slave
+config_interface -m_axi_offset slave

hls4ml/templates/vitis_accelerator/kernel_wrapper.h

@@ -7,4 +7,4 @@
 
 // hls-fpga-machine-learning accelerator io
 
-#endif
+#endif

hls4ml/templates/vitis_accelerator/kernel_wrapper_io_parallel.cpp

@@ -1,38 +1,39 @@
-#include "kernel_wrapper.h"
 #include "firmware/myproject.h"
+#include "kernel_wrapper.h"
 
 static void read_input(const /*IN_INTERFACE_TYPE*/ *in, in_buffer_t (&in_buf)[BATCHSIZE][DATA_SIZE_IN]) {
-  for (int i = 0; i < BATCHSIZE; i++) {
-      #pragma HLS PIPELINE
-      for(int j = 0; j < DATA_SIZE_IN; j++) { 
-        #pragma HLS UNROLL
-        in_buf[i][j] = /*IN_HW_QUANT*/in[i * DATA_SIZE_IN + j];
-      }
+    for (int i = 0; i < BATCHSIZE; i++) {
+        #pragma HLS PIPELINE
+        for (int j = 0; j < DATA_SIZE_IN; j++) {
+            #pragma HLS UNROLL
+            in_buf[i][j] = /*IN_HW_QUANT*/ in[i * DATA_SIZE_IN + j];
+        }
     }
 }
-static void run_inference(in_buffer_t (&in_buf)[BATCHSIZE][DATA_SIZE_IN], out_buffer_t (&out_buf)[BATCHSIZE][DATA_SIZE_OUT]) {
-  for (int i = 0; i < BATCHSIZE; i++) {
-      #pragma HLS DATAFLOW
-      myproject(in_buf[i],out_buf[i]);
+static void run_inference(in_buffer_t (&in_buf)[BATCHSIZE][DATA_SIZE_IN],
+                          out_buffer_t (&out_buf)[BATCHSIZE][DATA_SIZE_OUT]) {
+    for (int i = 0; i < BATCHSIZE; i++) {
+        #pragma HLS DATAFLOW
+        myproject(in_buf[i], out_buf[i]);
     }
 }
 static void write_result(/*OUT_INTERFACE_TYPE*/ *out, out_buffer_t (&out_buf)[BATCHSIZE][DATA_SIZE_OUT]) {
-  for (int i = 0; i < BATCHSIZE; i++) {
-    #pragma HLS PIPELINE
-    for (int j = 0; j < DATA_SIZE_OUT; j++) {
-      #pragma HLS UNROLL
-      out[i * DATA_SIZE_OUT + j] = /*OUT_HW_QUANT*/out_buf[i][j];
+    for (int i = 0; i < BATCHSIZE; i++) {
+        #pragma HLS PIPELINE
+        for (int j = 0; j < DATA_SIZE_OUT; j++) {
+            #pragma HLS UNROLL
+            out[i * DATA_SIZE_OUT + j] = /*OUT_HW_QUANT*/ out_buf[i][j];
+        }
     }
-  }
 }
 
 extern "C" {
-  /**
-    \brief HLS4ML Kernel Implementation 
-    \param in Input Vector
-    \param out Output Vector
+/**
+  \brief HLS4ML Kernel Implementation
+  \param in Input Vector
+  \param out Output Vector
 */
-  void kernel_wrapper(const /*IN_INTERFACE_TYPE*/ *in, /*OUT_INTERFACE_TYPE*/ *out) {
+void kernel_wrapper(const /*IN_INTERFACE_TYPE*/ *in, /*OUT_INTERFACE_TYPE*/ *out) {
     in_buffer_t in_buf[BATCHSIZE][DATA_SIZE_IN];
     out_buffer_t out_buf[BATCHSIZE][DATA_SIZE_OUT];
     #pragma HLS ARRAY_RESHAPE   variable=in_buf  complete dim=2
@@ -42,5 +43,5 @@ extern "C" {
     read_input(in, in_buf);
     run_inference(in_buf, out_buf);
     write_result(out, out_buf);
-  }
-}
+}
+}

hls4ml/templates/vitis_accelerator/kernel_wrapper_io_stream.cpp

@@ -1,43 +1,43 @@
-#include "kernel_wrapper.h"
 #include "firmware/myproject.h"
+#include "kernel_wrapper.h"
 
 static void read_input(const /*IN_INTERFACE_TYPE*/ *in, hls::stream<input_t> &input, int n) {
-  for (int i = 0; i < DATA_SIZE_IN; i++) {
-    #pragma HLS PIPELINE
-    input_t tmp;
-    for (int j = 0; j < NNET_ARRAY_DEPTH; j++) {
-      #pragma HLS UNROLL
-      tmp[j] = /*IN_HW_QUANT*/in[(n * DATA_SIZE_IN * NNET_ARRAY_DEPTH) + (i * NNET_ARRAY_DEPTH) + j];
+    for (int i = 0; i < DATA_SIZE_IN; i++) {
+        #pragma HLS PIPELINE
+        input_t tmp;
+        for (int j = 0; j < NNET_ARRAY_DEPTH; j++) {
+            #pragma HLS UNROLL
+            tmp[j] = /*IN_HW_QUANT*/ in[(n * DATA_SIZE_IN * NNET_ARRAY_DEPTH) + (i * NNET_ARRAY_DEPTH) + j];
+        }
+        input << tmp;
     }
-    input << tmp;
-  }
 }
 
 static void write_result(/*OUT_INTERFACE_TYPE*/ *out, hls::stream<result_t> &output, int n) {
-  result_t tmp = output.read();
-  for (int i = 0; i < DATA_SIZE_OUT; i++) {
-    #pragma HLS UNROLL
-    out[(n * DATA_SIZE_OUT) + i] = /*OUT_HW_QUANT*/tmp[i];
-  }
+    result_t tmp = output.read();
+    for (int i = 0; i < DATA_SIZE_OUT; i++) {
+        #pragma HLS UNROLL
+        out[(n * DATA_SIZE_OUT) + i] = /*OUT_HW_QUANT*/ tmp[i];
+    }
 }
 
 extern "C" {
-  /**
-    \brief HLS4ML Kernel Implementation 
-    \param in Input Vector
-    \param out Output Vector
+/**
+  \brief HLS4ML Kernel Implementation
+  \param in Input Vector
+  \param out Output Vector
 */
-  void kernel_wrapper(const /*IN_INTERFACE_TYPE*/ *in, /*OUT_INTERFACE_TYPE*/ *out) {
+void kernel_wrapper(const /*IN_INTERFACE_TYPE*/ *in, /*OUT_INTERFACE_TYPE*/ *out) {
     hls::stream<input_t> input("input");
     hls::stream<result_t> output("output");
     #pragma HLS STREAM variable=input depth=DATA_SIZE_IN
     #pragma HLS STREAM variable=output depth=1
-    
+
     for (int n = 0; n < BATCHSIZE; n++) {
-    #pragma HLS DATAFLOW          
-      read_input(in, input, n);
-      myproject(input, output);
-      write_result(out, output, n);
+        #pragma HLS DATAFLOW
+        read_input(in, input, n);
+        myproject(input, output);
+        write_result(out, output, n);
     }
-  }
-}
+}
+}

hls4ml/templates/vitis_accelerator/libs/DdrFpga.hpp

@@ -2,37 +2,32 @@
 
 #include "FpgaObj.hpp"
 
-template <class V, class W>
-class DdrFpga : public FpgaObj<V, W> {
- public:
+template <class V, class W> class DdrFpga : public FpgaObj<V, W> {
+  public:
     DdrFpga(int kernInputSize, int kernOutputSize, int numCU, int numThreads, int numEpochs)
-        : FpgaObj<V, W>(kernInputSize, kernOutputSize, numCU, numThreads, numEpochs) {
-    }
+        : FpgaObj<V, W>(kernInputSize, kernOutputSize, numCU, numThreads, numEpochs) {}
 
     void allocateHostMemory(int chan_per_port) {
         // Creating Buffer objects in Host memory
         /* ***NOTE*** When creating a Buffer with user pointer (CL_MEM_USE_HOST_PTR), under the hood, user pointer
         is used if it is properly aligned. when not aligned, runtime has no choice but to create
         its own host side Buffer. So it is recommended to use this allocator if user wishes to
-        create Buffer using CL_MEM_USE_HOST_PTR to align user buffer to page boundary. It will 
+        create Buffer using CL_MEM_USE_HOST_PTR to align user buffer to page boundary. It will
         ensure that user buffer is used when user creates Buffer/Mem object with CL_MEM_USE_HOST_PTR */
         size_t vector_size_in_bytes = sizeof(V) * this->_kernInputSize;
         size_t vector_size_out_bytes = sizeof(W) * this->_kernOutputSize;
         for (int ib = 0; ib < this->_numThreads; ib++) {
             for (int ik = 0; ik < this->_numCU; ik++) {
-                cl::Buffer buffer_in_tmp(this->context, 
-                        CL_MEM_USE_HOST_PTR | CL_MEM_READ_ONLY,
-                        vector_size_in_bytes,
-                        this->source_in.data() + ((ib*this->_numCU + ik) * this->_kernInputSize));
-                cl::Buffer buffer_out_tmp(this->context,
-                        CL_MEM_USE_HOST_PTR | CL_MEM_WRITE_ONLY,
-                        vector_size_out_bytes,
-                        this->source_hw_results.data() + ((ib*this->_numCU + ik) * this->_kernOutputSize));
+                cl::Buffer buffer_in_tmp(this->context, CL_MEM_USE_HOST_PTR | CL_MEM_READ_ONLY, vector_size_in_bytes,
+                                         this->source_in.data() + ((ib * this->_numCU + ik) * this->_kernInputSize));
+                cl::Buffer buffer_out_tmp(this->context, CL_MEM_USE_HOST_PTR | CL_MEM_WRITE_ONLY, vector_size_out_bytes,
+                                          this->source_hw_results.data() +
+                                              ((ib * this->_numCU + ik) * this->_kernOutputSize));
                 this->buffer_in.push_back(buffer_in_tmp);
                 this->buffer_out.push_back(buffer_out_tmp);
-                this->krnl_xil[ib*this->_numCU + ik].setArg(0, this->buffer_in[ib*this->_numCU + ik]);
-                this->krnl_xil[ib*this->_numCU + ik].setArg(1, this->buffer_out[ib*this->_numCU + ik]);
+                this->krnl_xil[ib * this->_numCU + ik].setArg(0, this->buffer_in[ib * this->_numCU + ik]);
+                this->krnl_xil[ib * this->_numCU + ik].setArg(1, this->buffer_out[ib * this->_numCU + ik]);
             }
         }
     }
-};
+};