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pwm_timer driver RC1:
 implement pwm_timer abstract layer implement pem_timer driver in iotdk board iotdk: sysconf: bug fix in PLL_CONF_VAL Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
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‎board/iotdk/configs/10/core_config.mk‎

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@@ -14,5 +14,6 @@ ONCHIP_IP_LIST ?= subsystem/gpio \
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subsystem/spi \
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subsystem/iic \
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designware/i2s \
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designware/sdio
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designware/sdio \
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designware/pwm_timer
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# dfss/dmac \

‎board/iotdk/drivers/ip/designware/pwm_timer/dw_pwm_timer_obj.c‎

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/* ------------------------------------------
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* Copyright (c) 2018, Synopsys, Inc. All rights reserved.
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1) Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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--------------------------------------------- */
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/**
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* \defgroup BOARD_EMSK_DRV_DW_PWM_TIMER_OBJ EMSK DW PWM_TIMER Object
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* \ingroup BOARD_IOTDK_DRIVER
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* \brief EMSK Designware UART Objects
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* \details
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* Realize the EMSK board uart object using Designware uart device driver,
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* only need to realize some Designware uart structures combine with EMSK uart
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* hardware resource. just like cpp class instantiation.
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*/
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/**
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* \file
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* \ingroup BOARD_EMSK_DRV_DW_UART_OBJ
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* \brief designware uart object instantiation on emsk
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*/
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#include "embARC_toolchain.h"
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#include "embARC_error.h"
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#include "iotdk_hardware.h"
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#include "dw_pwm_timer_obj.h"
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/**
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* \DW_PWM_TIMER_0 BOARD_EMSK_DRV_DW_UART_OBJ
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* @{
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*/
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/**
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* EMSK DesignWare PWM_TIMER Group 0 Object Instantiation
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*/
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#if (USE_DW_PWM_TIMER_0)
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#define PWM_TIMER_0_CH_0_INTNO 98 /*!< designware pwm_timer group 0 channel 0 interrupt number */
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static DEV_PWM_TIMER dw_pwm_timer_0; /*!< designware pwm_timer object */
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static DW_PWM_TIMER_CTRL dw_pwm_timer_0_ctrl; /*!< designware pwm_timer group 0 ctrl */
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static DEV_PWM_TIMER_HANDLER dw_pwm_timer_0_handler[DW_PWM_TIMER_0_CH_MAX_COUNT]; /*!< designware pwm_timer group 0 channels callback handler */
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static DEV_PWM_TIMER_MODE dw_pwm_timer_0_mode[DW_PWM_TIMER_0_CH_MAX_COUNT]; /*!< designware pwm_timer group 0 channels mode */
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static DW_PWM_TIMER_CH_ISR dw_pwm_timer_0_ch_isr = {
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DW_PWM_TIMER_0_CH_MAX_COUNT, dw_pwm_timer_0_handler
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};
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/** DesignWare PWM_TIMER 0 open */
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static int32_t dw_pwm_timer_0_open (void)
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{
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return dw_pwm_timer_open(&dw_pwm_timer_0);
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}
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/** DesignWare PWM_TIMER 0 close */
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static int32_t dw_pwm_timer_0_close (void)
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{
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return dw_pwm_timer_close(&dw_pwm_timer_0);
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}
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/** DesignWare PWM_TIMER 0 control */
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static int32_t dw_pwm_timer_0_control (uint32_t cmd, void *param)
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{
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return dw_pwm_timer_control(&dw_pwm_timer_0, cmd, param);
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}
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/** DesignWare PWM_TIMER 0 write */
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static int32_t dw_pwm_timer_0_write (uint32_t ch, uint32_t mode, uint32_t count_low, uint32_t count_high)
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{
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return dw_pwm_timer_write(&dw_pwm_timer_0, ch, mode, count_low, count_high);
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}
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/** DesignWare PWM_TIMER 0 read */
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static int32_t dw_pwm_timer_0_read (uint32_t ch, uint32_t *mode, uint32_t *count_low, uint32_t *count_high)
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{
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return dw_pwm_timer_read(&dw_pwm_timer_0, ch, mode, count_low, count_high);
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}
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/** DesignWare PWM_TIMER 0 interrupt routine */
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static void dw_pwm_timer_0_isr(void *ptr)
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{
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dw_pwm_timer_isr_handler(&dw_pwm_timer_0, ptr);
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}
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/** Install DesignWare PWM_TIMER 0 to system */
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static void dw_pwm_timer_0_install(void)
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{
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uint32_t i;
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DEV_PWM_TIMER *dw_pwm_timer_ptr = &dw_pwm_timer_0;
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DEV_PWM_TIMER_INFO *dw_pwm_timer_info_ptr = &(dw_pwm_timer_0.pwm_timer_info);
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DW_PWM_TIMER_CTRL_PTR dw_pwm_timer_ctrl_ptr = &(dw_pwm_timer_0_ctrl);
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/* Info init */
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dw_pwm_timer_info_ptr->pwm_timer_ctrl = (void *)dw_pwm_timer_ctrl_ptr;
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dw_pwm_timer_info_ptr->opn_cnt = 0;
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dw_pwm_timer_ctrl_ptr->id = DW_PWM_TIMER_0_ID;
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dw_pwm_timer_ctrl_ptr->regs = (DW_PWM_TIMER_REG_PTR)(BASE_ADDR_PWM);
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dw_pwm_timer_ctrl_ptr->intno = PWM_TIMER_0_CH_0_INTNO;
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dw_pwm_timer_ctrl_ptr->ch_num = DW_PWM_TIMER_0_CH_MAX_COUNT;
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dw_pwm_timer_ctrl_ptr->int_handler = dw_pwm_timer_0_isr;
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for (i=0; i < dw_pwm_timer_0_ch_isr.int_ch_max_cnt; i++) {
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dw_pwm_timer_0_ch_isr.int_ch_handler_ptr[i] = NULL;
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}
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dw_pwm_timer_ctrl_ptr->ch_isr = &(dw_pwm_timer_0_ch_isr);
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dw_pwm_timer_ctrl_ptr->mode = dw_pwm_timer_0_mode;
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/** PWM_TIMER dev init */
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dw_pwm_timer_ptr->pwm_timer_open = dw_pwm_timer_0_open;
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dw_pwm_timer_ptr->pwm_timer_close = dw_pwm_timer_0_close;
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dw_pwm_timer_ptr->pwm_timer_control = dw_pwm_timer_0_control;
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dw_pwm_timer_ptr->pwm_timer_write = dw_pwm_timer_0_write;
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dw_pwm_timer_ptr->pwm_timer_read = NULL;
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}
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#endif /* USE_DW_PWM_TIMER_0 */
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/** @} end of DW_PWM_TIMER_0 */
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/**
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* \brief install all pwm_timer objects
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* \note \b MUST be called during system init
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*/
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void dw_pwm_timer_all_install(void)
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{
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#if (USE_DW_PWM_TIMER_0)
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dw_pwm_timer_0_install();
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#endif
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}
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/** get one designware device structure */
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DEV_PWM_TIMER_PTR pwm_timer_get_dev(int32_t pwm_timer_id)
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{
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static uint32_t install_flag = 0;
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/* intall device objects */
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if (install_flag == 0) {
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install_flag = 1;
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dw_pwm_timer_all_install();
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}
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switch (pwm_timer_id) {
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#if (USE_DW_PWM_TIMER_0)
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case DW_PWM_TIMER_0_ID:
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return &dw_pwm_timer_0;
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break;
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#endif
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default:
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break;
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}
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return NULL;
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}
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‎board/iotdk/drivers/ip/designware/pwm_timer/dw_pwm_timer_obj.h‎

Lines changed: 53 additions & 0 deletions
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@@ -0,0 +1,53 @@
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/* ------------------------------------------
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* Copyright (c) 2018, Synopsys, Inc. All rights reserved.
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1) Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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10+
* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
20+
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23+
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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--------------------------------------------- */
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#ifndef _DW_PWM_TIMER_OBJ_H_
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#define _DW_PWM_TIMER_OBJ_H_
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#include "dw_pwm_timer.h"
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#define USE_DW_PWM_TIMER_0 1 /*!< enable use DesignWare PWM TIMER */
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#define DW_PWM_TIMER_0_ID 0
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#define DW_PWM_TIMER_0_CH_MAX_COUNT 6
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern DEV_PWM_TIMER_PTR pwm_timer_get_dev(int32_t pwm_timer_id);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DW_PWM_TIMER_OBJ_H_ */

‎board/iotdk/drivers/sysconf/sysconf.c‎

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@@ -46,7 +46,7 @@ typedef struct pll_conf {
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/* why m + 4 is required? from provided source code */
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#define PLL_CONF_VAL(n, m, od) \
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(((n) << PLLCON_BIT_OFFSET_N) | \
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((m + 4) << (PLLCON_BIT_OFFSET_M)) | \
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((m) << (PLLCON_BIT_OFFSET_M)) | \
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((od) << PLLCON_BIT_OFFSET_OD))
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‎board/iotdk/drivers/sysconf/sysconf.h‎

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@@ -164,6 +164,7 @@ extern void pll_conf_reg(uint32_t val);
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extern int32_t pll_fout_config(uint32_t freq);
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extern void ahb_clk_divisor(uint8_t div);
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extern void apb_clk_divisor(uint8_t div);
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extern void ahb_clk_enable(uint8_t dev);
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extern void ahb_clk_disable(uint8_t dev);
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extern void sdio_clk_divisor(uint8_t div);

‎board/iotdk/iotdk.h‎

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#include "drivers/ip/designware/i2s/dw_i2s_obj.h"
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#include "drivers/ip/designware/sdio/dw_sdio_obj.h"
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#include "drivers/ip/designware/pwm_timer/dw_pwm_timer_obj.h"
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#include "drivers/ip/subsystem/iic/dfss_iic_obj.h"
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#include "drivers/ip/subsystem/uart/dfss_uart_obj.h"
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#include "drivers/ip/subsystem/spi/dfss_spi_obj.h"

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