arcv: create a 32-bit integer multiply-add instruction pattern

The RHX core executes integer multiply-add sequences of the form:

mul r1,r2,r3
add r1,r1,r4

in 1 cycle due to macro-op fusion. This patch adds a
define_insn_and_split to recognize the above sequence and preserve it as
a single insn up until the post-reload split pass.

Since, due to a microarchitectural restriction, the output operand of
both instructions must be the same register, the insn_and_split pattern
has two alternatives corresponding to the following cases: (0) r1 is
different from r4, in which case the insn can be split to the sequence
above; (1) r1 and r4 are the same, in which case a temporary register
has to be used and there is no fusion.  Alternative (1) is discouraged
so that reload maximizes the number of instances where MAC fusion can be
applied.  Since RHX is a rv32im core, the pattern requires that the
target is 32-bit and supports multiplication.

In addition, the {u,}maddhisi3 expand is implemented for RHX to
convert the ( 16-bit x 16-bit + 32_bit ) WIDEN_MULT_PLUS_EXPR GIMPLE
operator to the aforementioned madd_split instruction directly.

Lastly, a very basic testcase is introduced to make sure that the
new patterns are sufficient to produce MAC-fusion-aware code.

No new dejagnu failures with RUNTESTFLAGS="CFLAGS_FOR_TARGET=-mtune=rhx
dg.exp".

Signed-off-by: Artemiy Volkov <artemiy@synopsys.com>

Author: artemiy-volkov

gcc/config/riscv/riscv.md

@@ -4502,7 +4502,35 @@
 	  (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand"))
 		   (sign_extend:SI (match_operand:HI 2 "register_operand")))
 	  (match_operand:SI 3 "register_operand")))]
-  "TARGET_XTHEADMAC"
+  "TARGET_XTHEADMAC || (riscv_is_micro_arch (arcv_rhx100)
+			&& !TARGET_64BIT && (TARGET_ZMMUL || TARGET_MUL))"
+  {
+    if (riscv_is_micro_arch (arcv_rhx100))
+      {
+	rtx tmp0 = gen_reg_rtx (SImode), tmp1 = gen_reg_rtx (SImode);
+	emit_insn (gen_extendhisi2 (tmp0, operands[1]));
+	emit_insn (gen_extendhisi2 (tmp1, operands[2]));
+	emit_insn (gen_madd_split_fused (operands[0], tmp0, tmp1, operands[3]));
+	DONE;
+      }
+  }
+)
+
+(define_expand "umaddhisi4"
+  [(set (match_operand:SI 0 "register_operand")
+	(plus:SI
+	  (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand"))
+		   (zero_extend:SI (match_operand:HI 2 "register_operand")))
+	  (match_operand:SI 3 "register_operand")))]
+  "riscv_is_micro_arch (arcv_rhx100)
+   && !TARGET_64BIT && (TARGET_ZMMUL || TARGET_MUL)"
+  {
+    rtx tmp0 = gen_reg_rtx (SImode), tmp1 = gen_reg_rtx (SImode);
+    emit_insn (gen_zero_extendhisi2 (tmp0, operands[1]));
+    emit_insn (gen_zero_extendhisi2 (tmp1, operands[2]));
+    emit_insn (gen_madd_split (operands[0], tmp0, tmp1, operands[3]));
+    DONE;
+  }
 )
 
 (define_expand "msubhisi4"
@@ -4514,6 +4542,33 @@
   "TARGET_XTHEADMAC"
 )
 
+(define_insn_and_split "madd_split"
+  [(set (match_operand:SI 0 "register_operand" "=&r,r")
+     (plus:SI
+	(mult:SI (match_operand:SI 1 "register_operand" "r,r")
+		 (match_operand:SI 2 "register_operand" "r,r"))
+	(match_operand:SI 3 "register_operand" "r,?0")))
+    (clobber (match_scratch:SI 4 "=&r,&r"))]
+  "riscv_is_micro_arch (rhx) && !TARGET_64BIT && (TARGET_ZMMUL || TARGET_MUL)"
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
+  "{
+     if (REGNO (operands[0]) == REGNO (operands[3]))
+       {
+	 emit_insn (gen_mulsi3 (operands[4], operands[1], operands[2]));
+	 emit_insn (gen_addsi3 (operands[0], operands[3], operands[4]));
+       }
+     else
+       {
+	 emit_insn (gen_mulsi3 (operands[0], operands[1], operands[2]));
+	 emit_insn (gen_addsi3 (operands[0], operands[0], operands[3]));
+       }
+    DONE;
+   }"
+  [(set_attr "type" "imul")]
+)
+
 ;; String compare with length insn.
 ;; Argument 0 is the target (result)
 ;; Argument 1 is the source1

gcc/testsuite/gcc.target/riscv/arcv-fusion-madd.c

@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv32 } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto" "-O0" } } */
+/* { dg-options "-mtune=arc-v-rhx-100-series -march=rv32im -mabi=ilp32" } */
+
+int
+f (int x, int y, int z, int v, int w)
+{
+  return x + y * z + v * w;
+}
+
+/* { dg-final { scan-assembler {\smul\s([ast][0-9]+),a1,a2\n\sadd\s\1,\1,a0\n\smul\sa0,a3,a4\n\sadd\sa0,a0,\1\n} } } */