arcv: Disable *<any_extract...>3 when fusion is available

This define_insn_and_split prevents *zero_extract_fused from being
selected.

Updated the test. It succeeded despite the fused case not being selected
because the right instructions were produced still.

Signed-off-by: Michiel Derhaeg <michiel@synopsys.com>

Author: MichielDerhaeg

gcc/config/riscv/iterators.md

@@ -218,6 +218,8 @@
 				      (zero_extract "srliw")])
 (define_code_attr extract_shift [(sign_extract "ashiftrt")
 				 (zero_extract "lshiftrt")])
+(define_code_attr is_zero_extract [(sign_extract "false")
+				                   (zero_extract "true")])
 
 ;; This code iterator allows the two right shift instructions to be
 ;; generated from the same template.

gcc/config/riscv/riscv.md

@@ -3101,6 +3101,7 @@
 ;; * Single-bit extraction (SFB)
 ;; * Extraction instruction th.ext(u) (XTheadBb)
 ;; * lshrsi3_extend_2 (see above)
+;; * Zero extraction fusion (ARC-V)
 (define_insn_and_split "*<any_extract:optab><GPR:mode>3"
   [(set (match_operand:GPR 0 "register_operand" "=r")
 	 (any_extract:GPR
@@ -3113,6 +3114,8 @@
      && (INTVAL (operands[2]) == 1))
    && !TARGET_XTHEADBB
    && !TARGET_XANDESPERF
+   && !(riscv_is_micro_arch (arcv_rhx100)
+        && <any_extract:is_zero_extract>)
    && !(TARGET_64BIT
         && (INTVAL (operands[3]) > 0)
         && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32))"
@@ -4600,7 +4603,7 @@
 		 (match_operand:SI 2 "register_operand" "r,r"))
 	(match_operand:SI 3 "register_operand" "r,?0"))))
     (clobber (match_scratch:SI 4 "=&r,&r"))]
-  "arcv_micro_arch_supports_fusion_p ()
+  "riscv_is_micro_arch (arcv_rhx100)
    && (TARGET_ZMMUL || TARGET_MUL)"
   {
      if (REGNO (operands[0]) == REGNO (operands[3]))

gcc/doc/riscv-mtune.texi

@@ -52,6 +52,8 @@ particular CPU name.  Permissible values for this option are:
 
 @samp{arc-v-rmx-100-series},
 
+@samp{arc-v-rhx-100-series},
+
 @samp{generic-ooo},
 
 @samp{size},

gcc/testsuite/gcc.target/riscv/arcv-fusion-xbfu.c

@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target rv32 } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto" "-O0" "-Oz" "-Os" } } */
-/* { dg-options "-mtune=arc-v-rhx-100-series -march=rv32im_zbs -mabi=ilp32" } */
+/* { dg-options "-mtune=arc-v-rhx-100-series -march=rv32im_zbs -mabi=ilp32 -dp" } */
 
 #define bit_extract(x,start,amt) (((x)>>(start)) & (~(0xffffffff << (amt))))
 
@@ -11,4 +11,4 @@ f (int x)
   return bit_extract(x,10,14) + bit_extract(x,1,1);
 }
 
-/* { dg-final { scan-assembler {\sslli\s([ast][0-9]+),a0,8\n\ssrli\s([ast][0-9]+),\1,18\n\sbexti\sa0,a0,1\n\sadd\sa0,\2,a0\n} } } */
+/* { dg-final { scan-assembler {\sslli\s([ast][0-9]+),a0,8.*zero_extract_fused\n\ssrli\s([ast][0-9]+),\1,18\n\sbexti\sa0,a0,1.*\n\sadd\sa0,\2,a0.*\n} } } */