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How to run ARC Linux kernel and debug (with MetaWare Debugger)

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Alexey Brodkin edited this page Jan 24, 2017 · 18 revisions

nSIM based Simulation

nSIM can simulate ARC770 and HS38x cores (and in reality almost any/all ARC processor and variants). ARC Linux runs well on NSIM. Infact the only difference in running Linux in simulation vs. hardware is limited number of peripherals supported in simulation. It is quite possible to run a same kernel binary built for HS38x cores in both nSIM and hardware platforms, provided the relevant drivers are included and right Device Tree is passed to kernel at the time of booting. ARC Linux however has "defconfigs" which automatically selects the right drivers as well as "embeds" the right device tree into kernel as well (as boot-loader is typically not available in simulation)

Command lines

Standalone nSIM (also free nSIM)

  • ARC HS38 defaut configuration (matches kernel "nsim_hs_defconfig")
nsimdrv -prop=nsim_isa_family=av2hs -prop=nsim_isa_core=1 -prop=chipid=0xffff -prop=nsim_isa_atomic_option=1 -prop=nsim_isa_ll64_option=1 -prop=nsim_mmu=4 -prop=mmu_pagesize=8192 -prop=mmu_super_pagesize=2097152 -prop=mmu_stlb_entries=16 -prop=mmu_ntlb_ways=4 -prop=mmu_ntlb_sets=128 -prop=icache=32768,64,4,0 -prop=dcache=16384,64,2,0 -prop=nsim_isa_shift_option=2 -prop=nsim_isa_swap_option=1 -prop=nsim_isa_bitscan_option=1 -prop=nsim_isa_sat=1 -prop=nsim_isa_div_rem_option=1 -prop=nsim_isa_mpy_option=9 -prop=nsim_isa_enable_timer_0=1 -prop=nsim_isa_enable_timer_1=1 -prop=nsim_isa_number_of_interrupts=32 -prop=nsim_isa_number_of_external_interrupts=32 -prop=isa_counters=1 -prop=nsim_isa_pct_counters=8 -prop=nsim_isa_pct_size=48 -prop=nsim_isa_pct_interrupt=1 -prop=nsim_mem-dev=uart0,base=0xc0fc1000,irq=24 -prop=nsim_isa_aps_feature=1 -prop=nsim_isa_num_actionpoints=4 vmlinux
  • ARC770 default configuration (matches kernel "nsim_700_defconfig")
nsimdrv -prop=nsim_isa_family=a700 -prop=nsim_isa_atomic_option=1 -prop=nsim_mmu=3 -prop=icache=32768,64,2,0 -prop=dcache=32768,64,4,0 -prop=nsim_isa_dpfp=none -prop=nsim_isa_shift_option=2 -prop=nsim_isa_swap_option=1 -prop=nsim_isa_bitscan_option=1 -prop=nsim_isa_sat=1 -prop=nsim_isa_mpy32=1 -prop=nsim_isa_enable_timer_0=1 -prop=nsim_isa_enable_timer_1=1 -prop=nsim_mem-dev=uart0 -prop=isa_counters=1 -prop=nsim_isa_pct_counters=8 -prop=nsim_isa_pct_size=48 vmlinux

nSIM via MDB

  • ARC770 defaut configuration (matches "nsim_700_defconfig")
mdb -a7 -nsim -Xlib -prop=nsim_mmu=3 -Xtimer0 -Xtimer1 -icache=16384,64,2,o -dcache=32768,64,4,o -prop=cpunum=0 -prop=nsim_mem-dev=uart0 -prop=nsim_sc_mem_range_end=0xc0fbffff -prop=nsim_isa_atomic_option=1 -prop=nsim_isa_num_actionpoints=8 -prop=nsim_isa_aps_feature=1 -OK -run -cl vmlinux
  • ARC HS38 default configuration (matches "nsim_hs_defconfig")
mdb -nsim -av2hs -prop=cpunum=0 -mmuv4 -Xrtc -Xatomic -Xtimer0 -Xtimer1 -Xmpyd -Xqmpyh -Xdiv_rem -toggle=deadbeef=1 -prop=nsim_mem-dev=uart0,base=0xc0fc1000,irq=24 -prop=mmu_pagesize=8192 -prop=mmu_super_pagesize=2097152 -prop=mmu_stlb_entries=16 -prop=mmu_ntlb_ways=4 -prop=mmu_ntlb_sets=128 -icache=16384,64,2,o -dcache=16384,64,4,o -prop=nsim_isa_aps_feature=1 -prop=nsim_isa_num_actionpoints=4 -prop=nsim_isa_ll64_option=1 -run -cl vmlinux
  • ARC HS38 multi-core configuration (matches "nsim_hs_smp_defconfig")
export NSIM_MULTICORE=1
mdb -pset=1 -psetname=core0 -prop=ident=0x00000050 -cmpd=soc -nsim -av2hs -core1 -prop=nsim_mem-dev=uart0,base=0xc0fc1000,irq=0,use_connect=1 -Xrtc -Xtimer0 -Xtimer1 -Xlib -Xll64 -Xatomic -Xunaligned -Xmacd -mmuv4 -prop=mmu_pagesize=8192 -prop=mmu_super_pagesize=32768 -prop=mmu_stlb_entries=16 -prop=mmu_ntlb_ways=4 -prop=mmu_ntlb_sets=128 -icache=16384,64,2,o -dcache=16384,64,4,o -on=nsim_print-sys-arch -prop=nsim_isa_num_actionpoints=4 -prop=nsim_isa_aps_feature=1 -on=nsim_mcip -on=nsim_mcip_idu -on=nsim_mcip_grtc -prop=nsim_mcip_version=2 -prop=isa_counters=1 -prop=nsim_isa_pct_counters=8 -prop=nsim_isa_pct_size=48 -prop=nsim_isa_pct_interrupt=1 -noprofile vmlinux
mdb -pset=2 -psetname=core1 -prop=ident=0x00000150 -cmpd=soc -nsim -av2hs -core1 -prop=nsim_mem-dev=uart0,base=0xc0fc1000,irq=0,use_connect=1 -Xrtc -Xtimer0 -Xtimer1 -Xlib -Xll64 -Xatomic -Xunaligned -Xmacd -mmuv4 -prop=mmu_pagesize=8192 -prop=mmu_super_pagesize=32768 -prop=mmu_stlb_entries=16 -prop=mmu_ntlb_ways=4 -prop=mmu_ntlb_sets=128 -icache=16384,64,2,o -dcache=16384,64,4,o -on=nsim_print-sys-arch -prop=nsim_isa_num_actionpoints=4 -prop=nsim_isa_aps_feature=1 -on=nsim_mcip -on=nsim_mcip_idu -on=nsim_mcip_grtc -prop=nsim_mcip_version=2 -prop=isa_counters=1 -prop=nsim_isa_pct_counters=8 -prop=nsim_isa_pct_size=48 -prop=nsim_isa_pct_interrupt=1 -noprofile vmlinux
mdb -multifiles=core0,core1 -cmpd=soc -run -cl

Note that all the ARConnect (MCIP) nsim_mcip_* properties have been deprecated. All the renamed nsim_connect_* properties, supported in nSIM K-2015.06 are no longer supported. New nsim_connect_* properties have been introduced to allow configuring of ARConnect 1.1 or 2.x. So if you have nsim version higher than K-2015.06 you should use following command lines:

export NSIM_MULTICORE=1
mdb -pset=1 -psetname=core0 -prop=ident=0x00000050 -cmpd=soc -nsim -av2hs -core1 -prop=nsim_mem-dev=uart0,base=0xc0fc1000,irq=0,use_connect=1 -Xrtc -Xtimer0 -Xtimer1 -Xlib -Xll64 -Xatomic -Xunaligned -Xmacd -mmuv4 -prop=mmu_pagesize=8192 -prop=mmu_super_pagesize=32768 -prop=mmu_stlb_entries=16 -prop=mmu_ntlb_ways=4 -prop=mmu_ntlb_sets=128 -icache=16384,64,2,o -dcache=16384,64,4,o -on=nsim_print-sys-arch -prop=nsim_isa_num_actionpoints=4 -prop=nsim_isa_aps_feature=1 -prop=nsim_connect=2 -prop=nsim_connect_idu=1 -prop=nsim_connect_gfrc=1 -prop=nsim_connect_ici=1 -prop=isa_counters=1 -prop=nsim_isa_pct_counters=8 -prop=nsim_isa_pct_size=48 -prop=nsim_isa_pct_interrupt=1 -noprofile vmlinux
mdb -pset=2 -psetname=core1 -prop=ident=0x00000150 -cmpd=soc -nsim -av2hs -core1 -prop=nsim_mem-dev=uart0,base=0xc0fc1000,irq=0,use_connect=1 -Xrtc -Xtimer0 -Xtimer1 -Xlib -Xll64 -Xatomic -Xunaligned -Xmacd -mmuv4 -prop=mmu_pagesize=8192 -prop=mmu_super_pagesize=32768 -prop=mmu_stlb_entries=16 -prop=mmu_ntlb_ways=4 -prop=mmu_ntlb_sets=128 -icache=16384,64,2,o -dcache=16384,64,4,o -on=nsim_print-sys-arch -prop=nsim_isa_num_actionpoints=4 -prop=nsim_isa_aps_feature=1 -prop=nsim_connect=2 -prop=nsim_connect_idu=1 -prop=nsim_connect_gfrc=1 -prop=nsim_connect_ici=1 -prop=isa_counters=1 -prop=nsim_isa_pct_counters=8 -prop=nsim_isa_pct_size=48 -prop=nsim_isa_pct_interrupt=1 -noprofile vmlinux
mdb -multifiles=core0,core1 -cmpd=soc -run -cl

Real hardware (ASIC/FPGA) via JTAG

Linux kernel being just an ordinary .elf (if built as vmlinux) could be debugged as a simple bare-metal application on real hardware target via JTAG.

Command lines

  • Single-core (either single-core HW or the first core of multi-core HW)
### Ashling Opella-XD
mdb -DLL=opxdarc.so -prop=jtag_frequency=12MHz -prop=jtag_optimise=1 -nooptions -OK -memxfersize=0x8000 vmlinux

### Digilent
mdb -digilent -prop=dig_speed=10000000 vmlinux
  • Dual-core SMP (first 2 cores of multi-core HW)
### Ashling Opella-XD
mdb -pset=1 -psetname=core0 -DLL=opxdarc.so -prop=jtag_frequency=12MHz -prop=jtag_optimise=1 -memxfersize=0x8000 vmlinux
mdb -pset=2 -psetname=core1 -DLL=opxdarc.so -prop=jtag_frequency=12MHz -prop=jtag_optimise=1 -prop=download=2 vmlinux
mdb -multifiles=core0,core1 -OK

### Digilent
mdb -pset=1 -psetname=core0 -digilent -prop=dig_speed=10000000 vmlinux
mdb -pset=2 -psetname=core1 -digilent -prop=download=2 vmlinux
mdb -multifiles=core0,core1 -OK
  • Quad-core SMP (first 4 cores of multi-core HW)
### Ashling Opella-XD
mdb -pset=1 -psetname=core0 -DLL=opxdarc.so -prop=jtag_frequency=12MHz -prop=jtag_optimise=1 -memxfersize=0x8000 vmlinux
mdb -pset=2 -psetname=core1 -DLL=opxdarc.so -prop=jtag_frequency=12MHz -prop=jtag_optimise=1 -prop=download=2 vmlinux
mdb -pset=3 -psetname=core2 -DLL=opxdarc.so -prop=jtag_frequency=12MHz -prop=jtag_optimise=1 -prop=download=2 vmlinux
mdb -pset=4 -psetname=core3 -DLL=opxdarc.so -prop=jtag_frequency=12MHz -prop=jtag_optimise=1 -prop=download=2 vmlinux
mdb -multifiles=core0,core1,core2,core3 -OK

### Digilent
mdb -pset=1 -psetname=core0 -digilent -prop=dig_speed=10000000 vmlinux
mdb -pset=2 -psetname=core1 -digilent -prop=download=2 vmlinux
mdb -pset=3 -psetname=core2 -digilent -prop=download=2 vmlinux
mdb -pset=4 -psetname=core3 -digilent -prop=download=2 vmlinux
mdb -multifiles=core0,core1,core2,core3 -OK

Notes

  • JTAG frequency should be at least 2 times lower than ARC core frequency. For 50MHz FPGA -jtag_frequency=12MHz is proven to work, while higher values may trigger problems like inconsistent memory values on elf load etc.

  • -memxfersize=0x8000 instructs debugger to send 32k blocks to Opella-XD.
    This significantly increases speed of elf download to target via JTAG.

  • -prop=jtag_optimise=1 turns off checking of the JTAG status registers by Opella-XD between successive JTAG read and write operations.
    This significantly increases speed of elf download to target via JTAG.

  • -prop=download=2 is required to let MDB know that this core will re-use elf loaded for other core

  • To escape specification of full path to opxdarc.so create a symlink to the .so in MW_HOME/MetaWare/arc/bin like this:

cd __path_to_opellaxdforarc_installation__
ln -s $PWD/opxdarc.so $MW_HOME/MetaWare/arc/bin/opxdarc.so
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