From 4b39a2dace743c78d79306c648c51a9a028c9d03 Mon Sep 17 00:00:00 2001 From: Phidias618 Date: Sun, 14 Sep 2025 21:46:27 +0200 Subject: [PATCH 1/6] Update CGB_Registers.md --- src/CGB_Registers.md | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/CGB_Registers.md b/src/CGB_Registers.md index a38441c0..72855f0b 100644 --- a/src/CGB_Registers.md +++ b/src/CGB_Registers.md @@ -124,6 +124,11 @@ Speed Mode). This allows for a transfer of 2280 bytes during VBlank, which is up to 142.5 tiles. +#### Status of the registers after the end of the transfer + +The source and destination address are both incremented by $10 bytes for each block of $10 bytes transfered after the transfer is done. +FF55 is set to $FF once the transfer ends. + ### VRAM Banks The CGB has twice the VRAM of the DMG, but it is banked and either bank From 333c116e515159b8d23cc0935dfffe70dc694639 Mon Sep 17 00:00:00 2001 From: Phidias618 Date: Sun, 14 Sep 2025 21:48:04 +0200 Subject: [PATCH 2/6] Update CGB_Registers.md --- src/CGB_Registers.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/CGB_Registers.md b/src/CGB_Registers.md index 72855f0b..718c01ef 100644 --- a/src/CGB_Registers.md +++ b/src/CGB_Registers.md @@ -126,7 +126,7 @@ This allows for a transfer of 2280 bytes during VBlank, which is up to 142.5 til #### Status of the registers after the end of the transfer -The source and destination address are both incremented by $10 bytes for each block of $10 bytes transfered after the transfer is done. +The source and destination address regisers are both incremented by $10 bytes for each block of $10 bytes transfered after the transfer is done. FF55 is set to $FF once the transfer ends. ### VRAM Banks From f03e6f7e686c3bbc74dd114c905aadfbb05d9ed4 Mon Sep 17 00:00:00 2001 From: Phidias618 Date: Sun, 14 Sep 2025 21:54:54 +0200 Subject: [PATCH 3/6] Update CGB_Registers.md --- src/CGB_Registers.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/CGB_Registers.md b/src/CGB_Registers.md index 718c01ef..9904d82f 100644 --- a/src/CGB_Registers.md +++ b/src/CGB_Registers.md @@ -127,7 +127,7 @@ This allows for a transfer of 2280 bytes during VBlank, which is up to 142.5 til #### Status of the registers after the end of the transfer The source and destination address regisers are both incremented by $10 bytes for each block of $10 bytes transfered after the transfer is done. -FF55 is set to $FF once the transfer ends. +FF55 is always equal to $FF once the transfer ends ### VRAM Banks From df09986441d7498eb81cf550751eebeb38531d4f Mon Sep 17 00:00:00 2001 From: Phidias618 Date: Fri, 26 Sep 2025 21:51:48 +0200 Subject: [PATCH 4/6] Moved the description of the state of the VRAM DMA source and destination registers --- src/CGB_Registers.md | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/src/CGB_Registers.md b/src/CGB_Registers.md index 9904d82f..c6ccc586 100644 --- a/src/CGB_Registers.md +++ b/src/CGB_Registers.md @@ -39,12 +39,14 @@ tested on Echo RAM, OAM, FEXX, IO and HRAM\]. Trying to specify a source address in VRAM will cause garbage to be copied. The four lower bits of this address will be ignored and treated as 0. +The address specified by those registers is incremented by $10 for each block of $10 bytes transfered successfully. #### FF53–FF54 — HDMA3, HDMA4 (CGB Mode only): VRAM DMA destination (high, low) \[write-only\] These two registers specify the address within 8000-9FF0 to which the data will be copied. Only bits 12-4 are respected; others are ignored. The four lower bits of this address will be ignored and treated as 0. +The address specified by those registers is incremented by $10 for each block of $10 bytes transfered successfully. #### FF55 — HDMA5 (CGB Mode only): VRAM DMA length/mode/start @@ -124,11 +126,6 @@ Speed Mode). This allows for a transfer of 2280 bytes during VBlank, which is up to 142.5 tiles. -#### Status of the registers after the end of the transfer - -The source and destination address regisers are both incremented by $10 bytes for each block of $10 bytes transfered after the transfer is done. -FF55 is always equal to $FF once the transfer ends - ### VRAM Banks The CGB has twice the VRAM of the DMG, but it is banked and either bank From d0e8aef09e97de0e2b3f9186b8f88584b929d50b Mon Sep 17 00:00:00 2001 From: Phidias618 <126189685+Phidias618@users.noreply.github.com> Date: Sat, 27 Sep 2025 13:43:50 +0200 Subject: [PATCH 5/6] Update src/CGB_Registers.md Co-authored-by: alloncm --- src/CGB_Registers.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/CGB_Registers.md b/src/CGB_Registers.md index c6ccc586..d7717a5b 100644 --- a/src/CGB_Registers.md +++ b/src/CGB_Registers.md @@ -39,14 +39,14 @@ tested on Echo RAM, OAM, FEXX, IO and HRAM\]. Trying to specify a source address in VRAM will cause garbage to be copied. The four lower bits of this address will be ignored and treated as 0. -The address specified by those registers is incremented by $10 for each block of $10 bytes transfered successfully. +The address specified by those registers is cached internally and incremented by $10 for each block of $10 bytes successfully transferred. The cached address persists until the registers are written again. #### FF53–FF54 — HDMA3, HDMA4 (CGB Mode only): VRAM DMA destination (high, low) \[write-only\] These two registers specify the address within 8000-9FF0 to which the data will be copied. Only bits 12-4 are respected; others are ignored. The four lower bits of this address will be ignored and treated as 0. -The address specified by those registers is incremented by $10 for each block of $10 bytes transfered successfully. +The address specified by those registers is cached internally and incremented by $10 for each block of $10 bytes successfully transferred. The cached address persists until the registers are written again. #### FF55 — HDMA5 (CGB Mode only): VRAM DMA length/mode/start From 7555343f70c248c2f75ee5b77aefc0e57e0ff85d Mon Sep 17 00:00:00 2001 From: Phidias618 Date: Sun, 19 Oct 2025 17:30:22 +0200 Subject: [PATCH 6/6] Update CGB_Registers.md --- src/CGB_Registers.md | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/src/CGB_Registers.md b/src/CGB_Registers.md index d7717a5b..50914e07 100644 --- a/src/CGB_Registers.md +++ b/src/CGB_Registers.md @@ -39,14 +39,33 @@ tested on Echo RAM, OAM, FEXX, IO and HRAM\]. Trying to specify a source address in VRAM will cause garbage to be copied. The four lower bits of this address will be ignored and treated as 0. -The address specified by those registers is cached internally and incremented by $10 for each block of $10 bytes successfully transferred. The cached address persists until the registers are written again. +After a transfer the address contained in this register pair is +by $10 for each block of $10 bytes transfered, these +registers being write-only, this can only be observed by doing another +transfer without updating these registers. + #### FF53–FF54 — HDMA3, HDMA4 (CGB Mode only): VRAM DMA destination (high, low) \[write-only\] These two registers specify the address within 8000-9FF0 to which the data will be copied. Only bits 12-4 are respected; others are ignored. The four lower bits of this address will be ignored and treated as 0. -The address specified by those registers is cached internally and incremented by $10 for each block of $10 bytes successfully transferred. The cached address persists until the registers are written again. + +#### State of the VRAM DMA source/destination registers after a transfer + +After a transfer, the source/destination registers are incremented by $10 +for each block of $10 bytes transfered. +Despite both the VRAM DMA source/destination registers being write-only, +knowing their state after a transfer can turn useful when performing +multiple transfer in a row. +For instance, a transfer of one large block is mostly equivalent to +multiple transfers of smaller blocks, without needing to update the source +nor the destination registers between each of the smaller transfers. +Another use case would be to fill VRAM with the same $10 bytes block repeated +all over, as only the source address register would need be updated after each +transfer, the destination register being automatically incremented by +the block size after each transfer. + #### FF55 — HDMA5 (CGB Mode only): VRAM DMA length/mode/start