Update UART loopback, added timing constraints and assignments.

Author: jakubcabal

example/ep4ce6_starter_board_assignments.qsf

@@ -0,0 +1,22 @@
+#-------------------------------------------------------------------------------
+# PROJECT: SIMPLE UART FOR FPGA
+#-------------------------------------------------------------------------------
+# MODULE:  CONSTRAINTS FOR EP4CE6 STARTER BOARD
+# AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
+# LICENSE: The MIT License (MIT), please read LICENSE file
+# WEBSITE: https://github.com/jakubcabal/uart-for-fpga
+#-------------------------------------------------------------------------------
+
+# GLOBAL CONSTRAINTS FOR EP4CE6 STARTER BOARD
+
+set_global_assignment -name FAMILY "Cyclone IV"
+set_global_assignment -name DEVICE EP4CE6E22C8
+set_global_assignment -name TOP_LEVEL_ENTITY UART_LOOPBACK
+
+# FPGA PINS ASSIGNMENT
+
+set_location_assignment PIN_91  -to CLK
+set_location_assignment PIN_25  -to RST
+
+set_location_assignment PIN_85  -to UART_TXD
+set_location_assignment PIN_86  -to UART_RXD

example/timing_constraints.sdc

@@ -0,0 +1,10 @@
+#-------------------------------------------------------------------------------
+# PROJECT: SIMPLE UART FOR FPGA
+#-------------------------------------------------------------------------------
+# MODULE:  TIMING CONSTRAINTS
+# AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
+# LICENSE: The MIT License (MIT), please read LICENSE file
+# WEBSITE: https://github.com/jakubcabal/uart-for-fpga
+#-------------------------------------------------------------------------------
+
+create_clock -name CLK50 -period 20.000 [get_ports {CLK}]

example/uart_loopback.vhd

@@ -4,7 +4,7 @@
 -- MODULE:  UART LOOPBACK EXAMPLE TOP MODULE
 -- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
 -- LICENSE: The MIT License (MIT), please read LICENSE file
--- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
+-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
 --------------------------------------------------------------------------------
 
 library IEEE;
@@ -16,52 +16,48 @@ use IEEE.NUMERIC_STD.ALL;
 
 entity UART_LOOPBACK is
     Generic (
-        CLK_FREQ   : integer := 50e6;   -- set system clock frequency in Hz
-        BAUD_RATE  : integer := 115200; -- baud rate value
-        PARITY_BIT : string  := "none"  -- legal values: "none", "even", "odd", "mark", "space"
+        CLK_FREQ      : integer := 50e6;   -- set system clock frequency in Hz
+        BAUD_RATE     : integer := 115200; -- baud rate value
+        PARITY_BIT    : string  := "none"; -- legal values: "none", "even", "odd", "mark", "space"
+        USE_DEBOUNCER : boolean := True    -- enable/disable debouncer
     );
     Port (
-        CLK        : in  std_logic; -- system clock
-        RST_N      : in  std_logic; -- low active synchronous reset
+        CLK      : in  std_logic; -- system clock
+        RST      : in  std_logic; -- high active synchronous reset
         -- UART INTERFACE
-        UART_TXD   : out std_logic;
-        UART_RXD   : in  std_logic;
-        -- DEBUG INTERFACE
-        BUSY       : out std_logic;
-        FRAME_ERR  : out std_logic
+        UART_TXD : out std_logic;
+        UART_RXD : in  std_logic
     );
 end UART_LOOPBACK;
 
 architecture FULL of UART_LOOPBACK is
 
-    signal data    : std_logic_vector(7 downto 0);
-    signal valid   : std_logic;
-    signal reset   : std_logic;
+    signal data  : std_logic_vector(7 downto 0);
+    signal valid : std_logic;
 
 begin
 
-	reset <= not RST_N;
-
 	uart_i: entity work.UART
     generic map (
-        CLK_FREQ    => CLK_FREQ,
-        BAUD_RATE   => BAUD_RATE,
-        PARITY_BIT  => PARITY_BIT
+        CLK_FREQ      => CLK_FREQ,
+        BAUD_RATE     => BAUD_RATE,
+        PARITY_BIT    => PARITY_BIT,
+        USE_DEBOUNCER => USE_DEBOUNCER
     )
     port map (
         CLK         => CLK,
-        RST         => reset,
+        RST         => RST,
         -- UART INTERFACE
         UART_TXD    => UART_TXD,
         UART_RXD    => UART_RXD,
         -- USER DATA OUTPUT INTERFACE
-        DATA_OUT    => data,
-        DATA_VLD    => valid,
-        FRAME_ERROR => FRAME_ERR,
+        DOUT        => data,
+        DOUT_VLD    => valid,
+        FRAME_ERROR => open,
         -- USER DATA INPUT INTERFACE
-        DATA_IN     => data,
-        DATA_SEND   => valid,
-        BUSY        => BUSY
+        DIN         => data,
+        DIN_VLD     => valid,
+        BUSY        => open
     );
 
 end FULL;

example/uart_loopback_tb.vhd

@@ -4,7 +4,7 @@
 -- MODULE:  TESTBANCH OF UART LOOPBACK EXAMPLE TOP MODULE
 -- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
 -- LICENSE: The MIT License (MIT), please read LICENSE file
--- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
+-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
 --------------------------------------------------------------------------------
 
 library IEEE;