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[AMDGPU] New llvm.amdgcn.wave.id intrinsic (#79325)
This is only valid on targets with architected SGPRs.
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‎llvm/include/llvm/IR/IntrinsicsAMDGPU.td‎

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@@ -2777,6 +2777,10 @@ class AMDGPULoadTr<LLVMType ptr_ty>:
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def int_amdgcn_global_load_tr : AMDGPULoadTr<global_ptr_ty>;
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// i32 @llvm.amdgcn.wave.id()
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def int_amdgcn_wave_id :
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DefaultAttrsIntrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable]>;
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//===----------------------------------------------------------------------===//
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// Deep learning intrinsics.
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp‎

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@@ -6883,6 +6883,23 @@ bool AMDGPULegalizerInfo::legalizeStackSave(MachineInstr &MI,
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return true;
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}
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bool AMDGPULegalizerInfo::legalizeWaveID(MachineInstr &MI,
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MachineIRBuilder &B) const {
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// With architected SGPRs, waveIDinGroup is in TTMP8[29:25].
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if (!ST.hasArchitectedSGPRs())
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return false;
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LLT S32 = LLT::scalar(32);
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Register DstReg = MI.getOperand(0).getReg();
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Register TTMP8 =
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getFunctionLiveInPhysReg(B.getMF(), B.getTII(), AMDGPU::TTMP8,
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AMDGPU::SReg_32RegClass, B.getDebugLoc(), S32);
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auto LSB = B.buildConstant(S32, 25);
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auto Width = B.buildConstant(S32, 5);
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B.buildUbfx(DstReg, TTMP8, LSB, Width);
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MI.eraseFromParent();
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return true;
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}
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bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
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MachineInstr &MI) const {
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MachineIRBuilder &B = Helper.MIRBuilder;
@@ -7005,6 +7022,8 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
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case Intrinsic::amdgcn_workgroup_id_z:
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return legalizePreloadedArgIntrin(MI, MRI, B,
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AMDGPUFunctionArgInfo::WORKGROUP_ID_Z);
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case Intrinsic::amdgcn_wave_id:
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return legalizeWaveID(MI, B);
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case Intrinsic::amdgcn_lds_kernel_id:
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return legalizePreloadedArgIntrin(MI, MRI, B,
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AMDGPUFunctionArgInfo::LDS_KERNEL_ID);

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h‎

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@@ -212,6 +212,7 @@ class AMDGPULegalizerInfo final : public LegalizerInfo {
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bool legalizeFPTruncRound(MachineInstr &MI, MachineIRBuilder &B) const;
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bool legalizeStackSave(MachineInstr &MI, MachineIRBuilder &B) const;
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bool legalizeWaveID(MachineInstr &MI, MachineIRBuilder &B) const;
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bool legalizeImageIntrinsic(
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MachineInstr &MI, MachineIRBuilder &B,

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp‎

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@@ -7920,6 +7920,18 @@ SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc,
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return Loads[0];
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}
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SDValue SITargetLowering::lowerWaveID(SelectionDAG &DAG, SDValue Op) const {
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// With architected SGPRs, waveIDinGroup is in TTMP8[29:25].
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if (!Subtarget->hasArchitectedSGPRs())
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return {};
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SDLoc SL(Op);
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MVT VT = MVT::i32;
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SDValue TTMP8 = CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
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AMDGPU::TTMP8, VT, SL);
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return DAG.getNode(AMDGPUISD::BFE_U32, SL, VT, TTMP8,
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DAG.getConstant(25, SL, VT), DAG.getConstant(5, SL, VT));
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}
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SDValue SITargetLowering::lowerWorkitemID(SelectionDAG &DAG, SDValue Op,
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unsigned Dim,
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const ArgDescriptor &Arg) const {
@@ -8090,6 +8102,8 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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case Intrinsic::amdgcn_workgroup_id_z:
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return getPreloadedValue(DAG, *MFI, VT,
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AMDGPUFunctionArgInfo::WORKGROUP_ID_Z);
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case Intrinsic::amdgcn_wave_id:
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return lowerWaveID(DAG, Op);
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case Intrinsic::amdgcn_lds_kernel_id: {
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if (MFI->isEntryFunction())
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return getLDSKernelId(DAG, DL);

‎llvm/lib/Target/AMDGPU/SIISelLowering.h‎

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@@ -80,6 +80,7 @@ class SITargetLowering final : public AMDGPUTargetLowering {
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SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
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unsigned NewOpcode) const;
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SDValue lowerWaveID(SelectionDAG &DAG, SDValue Op) const;
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SDValue lowerWorkitemID(SelectionDAG &DAG, SDValue Op, unsigned Dim,
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const ArgDescriptor &ArgDesc) const;
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‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll‎

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@@ -0,0 +1,61 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: not --crash llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -global-isel=0 -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GFX9-SDAG-ERR %s
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; RUN: not --crash llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -global-isel=1 -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GFX9-GISEL-ERR %s
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; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s
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; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s
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; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 %s
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; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 %s
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; GFX9-SDAG-ERR: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.wave.id
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; GFX9-GISEL-ERR: LLVM ERROR: unable to legalize instruction: {{.*}} = G_INTRINSIC intrinsic(@llvm.amdgcn.wave.id)
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define amdgpu_cs void @test_wave_id(ptr addrspace(1) %out) {
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; GFX9-LABEL: test_wave_id:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_bfe_u32 s0, ttmp8, 0x50019
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; GFX9-NEXT: v_mov_b32_e32 v2, s0
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; GFX9-NEXT: global_store_dword v[0:1], v2, off
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; GFX9-NEXT: s_endpgm
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;
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; GFX12-LABEL: test_wave_id:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_bfe_u32 s0, ttmp8, 0x50019
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: v_mov_b32_e32 v2, s0
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; GFX12-NEXT: global_store_b32 v[0:1], v2, off
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; GFX12-NEXT: s_nop 0
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; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-NEXT: s_endpgm
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%waveid = call i32 @llvm.amdgcn.wave.id()
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store i32 %waveid, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_gfx void @test_wave_id_callable(ptr addrspace(1) %out) {
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; GFX9-LABEL: test_wave_id_callable:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_bfe_u32 s34, ttmp8, 0x50019
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; GFX9-NEXT: v_mov_b32_e32 v2, s34
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; GFX9-NEXT: global_store_dword v[0:1], v2, off
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: test_wave_id_callable:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_bfe_u32 s0, ttmp8, 0x50019
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: v_mov_b32_e32 v2, s0
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; GFX12-NEXT: global_store_b32 v[0:1], v2, off
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%waveid = call i32 @llvm.amdgcn.wave.id()
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store i32 %waveid, ptr addrspace(1) %out
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ret void
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}
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declare i32 @llvm.amdgcn.wave.id()

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