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CodeGen: Remove TRI arguments from stack load/store hooks
This is directly available in TargetInstrInfo
1 parent df5d97f commit 571fa00

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62 files changed

+314
-344
lines changed

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1195,8 +1195,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
11951195
/// register spill instruction, part of prologue, during the frame lowering.
11961196
virtual void storeRegToStackSlot(
11971197
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
1198-
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
1199-
const TargetRegisterInfo *TRI, Register VReg,
1198+
bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
12001199
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const {
12011200
llvm_unreachable("Target didn't implement "
12021201
"TargetInstrInfo::storeRegToStackSlot!");
@@ -1214,8 +1213,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
12141213
/// register reload instruction, part of epilogue, during the frame lowering.
12151214
virtual void loadRegFromStackSlot(
12161215
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
1217-
int FrameIndex, const TargetRegisterClass *RC,
1218-
const TargetRegisterInfo *TRI, Register VReg,
1216+
int FrameIndex, const TargetRegisterClass *RC, Register VReg,
12191217
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const {
12201218
llvm_unreachable("Target didn't implement "
12211219
"TargetInstrInfo::loadRegFromStackSlot!");

‎llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -420,7 +420,7 @@ class StatepointState {
420420

421421
LLVM_DEBUG(dbgs() << "Insert spill before " << *InsertBefore);
422422
TII.storeRegToStackSlot(*MI.getParent(), InsertBefore, Reg, IsKill, FI,
423-
RC, &TRI, Register());
423+
RC, Register());
424424
}
425425
}
426426

@@ -429,15 +429,15 @@ class StatepointState {
429429
const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
430430
int FI = RegToSlotIdx[Reg];
431431
if (It != MBB->end()) {
432-
TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI, Register());
432+
TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, Register());
433433
return;
434434
}
435435

436436
// To insert reload at the end of MBB, insert it before last instruction
437437
// and then swap them.
438438
assert(!MBB->empty() && "Empty block");
439439
--It;
440-
TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI, Register());
440+
TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, Register());
441441
MachineInstr *Reload = It->getPrevNode();
442442
int Dummy = 0;
443443
(void)Dummy;

‎llvm/lib/CodeGen/InlineSpiller.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -473,7 +473,7 @@ bool InlineSpiller::hoistSpillInsideBB(LiveInterval &SpillLI,
473473
MachineInstrSpan MIS(MII, MBB);
474474
// Insert spill without kill flag immediately after def.
475475
TII.storeRegToStackSlot(*MBB, MII, SrcReg, false, StackSlot,
476-
MRI.getRegClass(SrcReg), &TRI, Register());
476+
MRI.getRegClass(SrcReg), Register());
477477
LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MII);
478478
for (const MachineInstr &MI : make_range(MIS.begin(), MII))
479479
getVDefInterval(MI, LIS);
@@ -1119,7 +1119,7 @@ void InlineSpiller::insertReload(Register NewVReg,
11191119

11201120
MachineInstrSpan MIS(MI, &MBB);
11211121
TII.loadRegFromStackSlot(MBB, MI, NewVReg, StackSlot,
1122-
MRI.getRegClass(NewVReg), &TRI, Register());
1122+
MRI.getRegClass(NewVReg), Register());
11231123

11241124
LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MI);
11251125

@@ -1155,7 +1155,7 @@ void InlineSpiller::insertSpill(Register NewVReg, bool isKill,
11551155

11561156
if (IsRealSpill)
11571157
TII.storeRegToStackSlot(MBB, SpillBefore, NewVReg, isKill, StackSlot,
1158-
MRI.getRegClass(NewVReg), &TRI, Register());
1158+
MRI.getRegClass(NewVReg), Register());
11591159
else
11601160
// Don't spill undef value.
11611161
// Anything works for undef, in particular keeping the memory
@@ -1729,7 +1729,7 @@ void HoistSpillHelper::hoistAllSpills() {
17291729
MachineBasicBlock::iterator MII = IPA.getLastInsertPointIter(OrigLI, *BB);
17301730
MachineInstrSpan MIS(MII, BB);
17311731
TII.storeRegToStackSlot(*BB, MII, LiveReg, false, Slot,
1732-
MRI.getRegClass(LiveReg), &TRI, Register());
1732+
MRI.getRegClass(LiveReg), Register());
17331733
LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MII);
17341734
for (const MachineInstr &MI : make_range(MIS.begin(), MII))
17351735
getVDefInterval(MI, LIS);

‎llvm/lib/CodeGen/RegAllocFast.cpp‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -594,8 +594,7 @@ void RegAllocFastImpl::spill(MachineBasicBlock::iterator Before,
594594
LLVM_DEBUG(dbgs() << " to stack slot #" << FI << '\n');
595595

596596
const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
597-
TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, TRI,
598-
VirtReg);
597+
TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, VirtReg);
599598
++NumStores;
600599

601600
MachineBasicBlock::iterator FirstTerm = MBB->getFirstTerminator();
@@ -652,7 +651,7 @@ void RegAllocFastImpl::reload(MachineBasicBlock::iterator Before,
652651
<< printReg(PhysReg, TRI) << '\n');
653652
int FI = getStackSpaceFor(VirtReg);
654653
const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
655-
TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, TRI, VirtReg);
654+
TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, VirtReg);
656655
++NumLoads;
657656
}
658657

@@ -1123,7 +1122,7 @@ bool RegAllocFastImpl::defineVirtReg(MachineInstr &MI, unsigned OpNum,
11231122
if (MO.isMBB()) {
11241123
MachineBasicBlock *Succ = MO.getMBB();
11251124
TII->storeRegToStackSlot(*Succ, Succ->begin(), PhysReg, Kill, FI,
1126-
&RC, TRI, VirtReg);
1125+
&RC, VirtReg);
11271126
++NumStores;
11281127
Succ->addLiveIn(PhysReg);
11291128
}

‎llvm/lib/CodeGen/RegisterScavenging.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -276,14 +276,14 @@ RegScavenger::spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
276276
": Cannot scavenge register without an emergency "
277277
"spill slot!");
278278
}
279-
TII->storeRegToStackSlot(*MBB, Before, Reg, true, FI, &RC, TRI, Register());
279+
TII->storeRegToStackSlot(*MBB, Before, Reg, true, FI, &RC, Register());
280280
MachineBasicBlock::iterator II = std::prev(Before);
281281

282282
unsigned FIOperandNum = getFrameIndexOperandNum(*II);
283283
TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
284284

285285
// Restore the scavenged register before its use (or first terminator).
286-
TII->loadRegFromStackSlot(*MBB, UseMI, Reg, FI, &RC, TRI, Register());
286+
TII->loadRegFromStackSlot(*MBB, UseMI, Reg, FI, &RC, Register());
287287
II = std::prev(UseMI);
288288

289289
FIOperandNum = getFrameIndexOperandNum(*II);

‎llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -198,7 +198,7 @@ void TargetFrameLowering::spillCalleeSavedRegister(
198198
} else {
199199
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
200200
TII->storeRegToStackSlot(SaveBlock, MI, Reg, true, CS.getFrameIdx(), RC,
201-
TRI, Register());
201+
Register());
202202
}
203203
}
204204

@@ -212,8 +212,7 @@ void TargetFrameLowering::restoreCalleeSavedRegister(
212212
.addReg(CS.getDstReg(), getKillRegState(true));
213213
} else {
214214
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
215-
TII->loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI,
216-
Register());
215+
TII->loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, Register());
217216
assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!");
218217
}
219218
}

‎llvm/lib/CodeGen/TargetInstrInfo.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -795,11 +795,11 @@ MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
795795
// code.
796796
BuildMI(*MBB, Pos, MI.getDebugLoc(), get(TargetOpcode::KILL)).add(MO);
797797
} else {
798-
storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, &TRI,
798+
storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC,
799799
Register());
800800
}
801801
} else
802-
loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, &TRI, Register());
802+
loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, Register());
803803

804804
return &*--Pos;
805805
}

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -5616,7 +5616,6 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
56165616
MachineBasicBlock::iterator MBBI,
56175617
Register SrcReg, bool isKill, int FI,
56185618
const TargetRegisterClass *RC,
5619-
const TargetRegisterInfo *TRI,
56205619
Register VReg,
56215620
MachineInstr::MIFlag Flags) const {
56225621
MachineFunction &MF = *MBB.getParent();
@@ -5630,7 +5629,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
56305629
bool Offset = true;
56315630
MCRegister PNRReg = MCRegister::NoRegister;
56325631
unsigned StackID = TargetStackID::Default;
5633-
switch (TRI->getSpillSize(*RC)) {
5632+
switch (RI.getSpillSize(*RC)) {
56345633
case 1:
56355634
if (AArch64::FPR8RegClass.hasSubClassEq(RC))
56365635
Opc = AArch64::STRBui;
@@ -5793,10 +5792,12 @@ static void loadRegPairFromStackSlot(const TargetRegisterInfo &TRI,
57935792
.addMemOperand(MMO);
57945793
}
57955794

5796-
void AArch64InstrInfo::loadRegFromStackSlot(
5797-
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg,
5798-
int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
5799-
Register VReg, MachineInstr::MIFlag Flags) const {
5795+
void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
5796+
MachineBasicBlock::iterator MBBI,
5797+
Register DestReg, int FI,
5798+
const TargetRegisterClass *RC,
5799+
Register VReg,
5800+
MachineInstr::MIFlag Flags) const {
58005801
MachineFunction &MF = *MBB.getParent();
58015802
MachineFrameInfo &MFI = MF.getFrameInfo();
58025803
MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
@@ -5808,7 +5809,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
58085809
bool Offset = true;
58095810
unsigned StackID = TargetStackID::Default;
58105811
Register PNRReg = MCRegister::NoRegister;
5811-
switch (TRI->getSpillSize(*RC)) {
5812+
switch (TRI.getSpillSize(*RC)) {
58125813
case 1:
58135814
if (AArch64::FPR8RegClass.hasSubClassEq(RC))
58145815
Opc = AArch64::LDRBui;
@@ -6444,10 +6445,10 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
64446445
"Mismatched register size in non subreg COPY");
64456446
if (IsSpill)
64466447
storeRegToStackSlot(MBB, InsertPt, SrcReg, SrcMO.isKill(), FrameIndex,
6447-
getRegClass(SrcReg), &TRI, Register());
6448+
getRegClass(SrcReg), Register());
64486449
else
64496450
loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex,
6450-
getRegClass(DstReg), &TRI, Register());
6451+
getRegClass(DstReg), Register());
64516452
return &*--InsertPt;
64526453
}
64536454

@@ -6465,8 +6466,7 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
64656466
assert(SrcMO.getSubReg() == 0 &&
64666467
"Unexpected subreg on physical register");
64676468
storeRegToStackSlot(MBB, InsertPt, AArch64::XZR, SrcMO.isKill(),
6468-
FrameIndex, &AArch64::GPR64RegClass, &TRI,
6469-
Register());
6469+
FrameIndex, &AArch64::GPR64RegClass, Register());
64706470
return &*--InsertPt;
64716471
}
64726472

@@ -6500,7 +6500,7 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
65006500
assert(TRI.getRegSizeInBits(*getRegClass(SrcReg)) ==
65016501
TRI.getRegSizeInBits(*FillRC) &&
65026502
"Mismatched regclass size on folded subreg COPY");
6503-
loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex, FillRC, &TRI,
6503+
loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex, FillRC,
65046504
Register());
65056505
MachineInstr &LoadMI = *--InsertPt;
65066506
MachineOperand &LoadDst = LoadMI.getOperand(0);

‎llvm/lib/Target/AArch64/AArch64InstrInfo.h‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -353,14 +353,13 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
353353

354354
void storeRegToStackSlot(
355355
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
356-
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
357-
const TargetRegisterInfo *TRI, Register VReg,
356+
bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
358357
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
359358

360359
void loadRegFromStackSlot(
361360
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
362361
Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
363-
const TargetRegisterInfo *TRI, Register VReg,
362+
Register VReg,
364363
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
365364

366365
// This tells target independent code that it is okay to pass instructions

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1668,8 +1668,7 @@ unsigned SIInstrInfo::getVectorRegSpillSaveOpcode(
16681668

16691669
void SIInstrInfo::storeRegToStackSlot(
16701670
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
1671-
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
1672-
const TargetRegisterInfo *TRI, Register VReg,
1671+
bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
16731672
MachineInstr::MIFlag Flags) const {
16741673
MachineFunction *MF = MBB.getParent();
16751674
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
@@ -1681,7 +1680,7 @@ void SIInstrInfo::storeRegToStackSlot(
16811680
MachineMemOperand *MMO = MF->getMachineMemOperand(
16821681
PtrInfo, MachineMemOperand::MOStore, FrameInfo.getObjectSize(FrameIndex),
16831682
FrameInfo.getObjectAlign(FrameIndex));
1684-
unsigned SpillSize = TRI->getSpillSize(*RC);
1683+
unsigned SpillSize = RI.getSpillSize(*RC);
16851684

16861685
MachineRegisterInfo &MRI = MF->getRegInfo();
16871686
if (RI.isSGPRClass(RC)) {
@@ -1863,14 +1862,13 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
18631862
MachineBasicBlock::iterator MI,
18641863
Register DestReg, int FrameIndex,
18651864
const TargetRegisterClass *RC,
1866-
const TargetRegisterInfo *TRI,
18671865
Register VReg,
18681866
MachineInstr::MIFlag Flags) const {
18691867
MachineFunction *MF = MBB.getParent();
18701868
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
18711869
MachineFrameInfo &FrameInfo = MF->getFrameInfo();
18721870
const DebugLoc &DL = MBB.findDebugLoc(MI);
1873-
unsigned SpillSize = TRI->getSpillSize(*RC);
1871+
unsigned SpillSize = RI.getSpillSize(*RC);
18741872

18751873
MachinePointerInfo PtrInfo
18761874
= MachinePointerInfo::getFixedStack(*MF, FrameIndex);

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