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arsenmarsenm
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ARM: Remove TRI argument from AddDReg
1 parent 37b57b5 commit 6bde21f

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3 files changed

+48
-49
lines changed

3 files changed

+48
-49
lines changed

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp‎

Lines changed: 43 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -929,15 +929,15 @@ ARMBaseInstrInfo::describeLoadedValue(const MachineInstr &MI,
929929
return TargetInstrInfo::describeLoadedValue(MI, Reg);
930930
}
931931

932-
const MachineInstrBuilder &
933-
ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
934-
unsigned SubIdx, unsigned State,
935-
const TargetRegisterInfo *TRI) const {
932+
const MachineInstrBuilder &ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB,
933+
unsigned Reg,
934+
unsigned SubIdx,
935+
unsigned State) const {
936936
if (!SubIdx)
937937
return MIB.addReg(Reg, State);
938938

939939
if (Register::isPhysicalRegister(Reg))
940-
return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
940+
return MIB.addReg(getRegisterInfo().getSubReg(Reg, SubIdx), State);
941941
return MIB.addReg(Reg, State, SubIdx);
942942
}
943943

@@ -1011,8 +1011,8 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
10111011
} else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
10121012
if (Subtarget.hasV5TEOps()) {
10131013
MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD));
1014-
AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
1015-
AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
1014+
AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill));
1015+
AddDReg(MIB, SrcReg, ARM::gsub_1, 0);
10161016
MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
10171017
.add(predOps(ARMCC::AL));
10181018
} else {
@@ -1022,8 +1022,8 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
10221022
.addFrameIndex(FI)
10231023
.addMemOperand(MMO)
10241024
.add(predOps(ARMCC::AL));
1025-
AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
1026-
AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
1025+
AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill));
1026+
AddDReg(MIB, SrcReg, ARM::gsub_1, 0);
10271027
}
10281028
} else
10291029
llvm_unreachable("Unknown reg class!");
@@ -1073,9 +1073,9 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
10731073
.addFrameIndex(FI)
10741074
.add(predOps(ARMCC::AL))
10751075
.addMemOperand(MMO);
1076-
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1077-
MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1078-
AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1076+
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill));
1077+
MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0);
1078+
AddDReg(MIB, SrcReg, ARM::dsub_2, 0);
10791079
}
10801080
} else
10811081
llvm_unreachable("Unknown reg class!");
@@ -1105,10 +1105,10 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
11051105
.addFrameIndex(FI)
11061106
.add(predOps(ARMCC::AL))
11071107
.addMemOperand(MMO);
1108-
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1109-
MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1110-
MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1111-
AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1108+
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill));
1109+
MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0);
1110+
MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0);
1111+
AddDReg(MIB, SrcReg, ARM::dsub_3, 0);
11121112
}
11131113
} else
11141114
llvm_unreachable("Unknown reg class!");
@@ -1125,14 +1125,14 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
11251125
.addFrameIndex(FI)
11261126
.add(predOps(ARMCC::AL))
11271127
.addMemOperand(MMO);
1128-
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1129-
MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1130-
MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1131-
MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1132-
MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
1133-
MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
1134-
MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
1135-
AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
1128+
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill));
1129+
MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0);
1130+
MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0);
1131+
MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0);
1132+
MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0);
1133+
MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0);
1134+
MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0);
1135+
AddDReg(MIB, SrcReg, ARM::dsub_7, 0);
11361136
} else
11371137
llvm_unreachable("Unknown reg class!");
11381138
break;
@@ -1272,8 +1272,8 @@ void ARMBaseInstrInfo::loadRegFromStackSlot(
12721272

12731273
if (Subtarget.hasV5TEOps()) {
12741274
MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1275-
AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1276-
AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1275+
AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead);
1276+
AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead);
12771277
MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
12781278
.add(predOps(ARMCC::AL));
12791279
} else {
@@ -1283,8 +1283,8 @@ void ARMBaseInstrInfo::loadRegFromStackSlot(
12831283
.addFrameIndex(FI)
12841284
.addMemOperand(MMO)
12851285
.add(predOps(ARMCC::AL));
1286-
MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1287-
MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1286+
MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead);
1287+
MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead);
12881288
}
12891289

12901290
if (DestReg.isPhysical())
@@ -1330,9 +1330,9 @@ void ARMBaseInstrInfo::loadRegFromStackSlot(
13301330
.addFrameIndex(FI)
13311331
.addMemOperand(MMO)
13321332
.add(predOps(ARMCC::AL));
1333-
MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1334-
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1335-
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1333+
MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead);
1334+
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead);
1335+
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead);
13361336
if (DestReg.isPhysical())
13371337
MIB.addReg(DestReg, RegState::ImplicitDefine);
13381338
}
@@ -1359,10 +1359,10 @@ void ARMBaseInstrInfo::loadRegFromStackSlot(
13591359
.addFrameIndex(FI)
13601360
.add(predOps(ARMCC::AL))
13611361
.addMemOperand(MMO);
1362-
MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1363-
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1364-
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1365-
MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1362+
MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead);
1363+
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead);
1364+
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead);
1365+
MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead);
13661366
if (DestReg.isPhysical())
13671367
MIB.addReg(DestReg, RegState::ImplicitDefine);
13681368
}
@@ -1380,14 +1380,14 @@ void ARMBaseInstrInfo::loadRegFromStackSlot(
13801380
.addFrameIndex(FI)
13811381
.add(predOps(ARMCC::AL))
13821382
.addMemOperand(MMO);
1383-
MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1384-
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1385-
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1386-
MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1387-
MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1388-
MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1389-
MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1390-
MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1383+
MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead);
1384+
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead);
1385+
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead);
1386+
MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead);
1387+
MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead);
1388+
MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead);
1389+
MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead);
1390+
MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead);
13911391
if (DestReg.isPhysical())
13921392
MIB.addReg(DestReg, RegState::ImplicitDefine);
13931393
} else

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.h‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -240,8 +240,7 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
240240
const MachineInstr &Orig) const override;
241241

242242
const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
243-
unsigned SubIdx, unsigned State,
244-
const TargetRegisterInfo *TRI) const;
243+
unsigned SubIdx, unsigned State) const;
245244

246245
bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
247246
const MachineRegisterInfo *MRI) const override;

‎llvm/lib/Target/ARM/Thumb2InstrInfo.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -197,8 +197,8 @@ void Thumb2InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
197197
}
198198

199199
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
200-
AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
201-
AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
200+
AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill));
201+
AddDReg(MIB, SrcReg, ARM::gsub_1, 0);
202202
MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));
203203
return;
204204
}
@@ -238,8 +238,8 @@ void Thumb2InstrInfo::loadRegFromStackSlot(
238238
}
239239

240240
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
241-
AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
242-
AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
241+
AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead);
242+
AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead);
243243
MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO).add(predOps(ARMCC::AL));
244244

245245
if (DestReg.isPhysical())

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