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[mlir][spirv] Enable validation of selection and phi tests (#166794)
Some of the test cases are failing as they introduce unstructured control flow. It would be good to catch this in MLIR, but I am not sure it is currently feasible. We could enforce the conditional branch to always be in `spirv.mlir.selection` however from my perspective it will break our downstream project as we rely on unstructured control flow, i.e., the control flow graph is structured but we do not use `spirv.mlir.selection` and `spirv.mlir.loop` as they do not currently support early exists. It seems that the support for early exists is slowly coming into MLIR so we probably can revise what is being enforced regarding control flow ops in the future.
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mlir/test/Target/SPIRV/phi.mlir

Lines changed: 50 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,10 @@
11
// RUN: mlir-translate -no-implicit-module -split-input-file -test-spirv-roundtrip %s | FileCheck %s
22

3+
// RUN: %if spirv-tools %{ rm -rf %t %}
4+
// RUN: %if spirv-tools %{ mkdir %t %}
5+
// RUN: %if spirv-tools %{ mlir-translate --no-implicit-module --serialize-spirv --split-input-file --spirv-save-validation-files-with-prefix=%t/module %s %}
6+
// RUN: %if spirv-tools %{ spirv-val %t %}
7+
38
// Test branch with one block argument
49

510
spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], []> {
@@ -295,15 +300,26 @@ spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], []> {
295300
%true = spirv.Constant true
296301
%zero = spirv.Constant 0 : i32
297302
%one = spirv.Constant 1 : i32
303+
spirv.mlir.selection {
298304
// CHECK: spirv.BranchConditional %{{.*}}, ^[[true1:.*]](%{{.*}}, %{{.*}} : i32, i32), ^[[false1:.*]]
299-
spirv.BranchConditional %true, ^true1(%zero, %zero: i32, i32), ^false1
305+
spirv.BranchConditional %true, ^true1(%zero, %zero: i32, i32), ^false1
300306
// CHECK: [[true1]](%{{.*}}: i32, %{{.*}}: i32)
301-
^true1(%arg0: i32, %arg1: i32):
302-
spirv.Return
307+
^true1(%arg0: i32, %arg1: i32):
308+
spirv.Return
303309
// CHECK: [[false1]]:
304-
^false1:
310+
^false1:
311+
spirv.Return
312+
^merge:
313+
spirv.mlir.merge
314+
}
315+
316+
spirv.Return
317+
}
318+
319+
spirv.func @main() -> () "None" {
305320
spirv.Return
306321
}
322+
spirv.EntryPoint "GLCompute" @main
307323
}
308324

309325
// -----
@@ -314,15 +330,26 @@ spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], []> {
314330
%true = spirv.Constant true
315331
%zero = spirv.Constant 0 : i32
316332
%one = spirv.Constant 1 : i32
333+
spirv.mlir.selection {
317334
// CHECK: spirv.BranchConditional %{{.*}}, ^[[true1:.*]], ^[[false1:.*]](%{{.*}}, %{{.*}} : i32, i32)
318-
spirv.BranchConditional %true, ^true1, ^false1(%zero, %zero: i32, i32)
335+
spirv.BranchConditional %true, ^true1, ^false1(%zero, %zero: i32, i32)
319336
// CHECK: [[true1]]:
320-
^true1:
321-
spirv.Return
337+
^true1:
338+
spirv.Return
322339
// CHECK: [[false1]](%{{.*}}: i32, %{{.*}}: i32):
323-
^false1(%arg0: i32, %arg1: i32):
340+
^false1(%arg0: i32, %arg1: i32):
341+
spirv.Return
342+
^merge:
343+
spirv.mlir.merge
344+
}
345+
346+
spirv.Return
347+
}
348+
349+
spirv.func @main() -> () "None" {
324350
spirv.Return
325351
}
352+
spirv.EntryPoint "GLCompute" @main
326353
}
327354

328355
// -----
@@ -333,13 +360,24 @@ spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], []> {
333360
%true = spirv.Constant true
334361
%zero = spirv.Constant 0 : i32
335362
%one = spirv.Constant 1 : i32
363+
spirv.mlir.selection {
336364
// CHECK: spirv.BranchConditional %{{.*}}, ^[[true1:.*]](%{{.*}} : i32), ^[[false1:.*]](%{{.*}}, %{{.*}} : i32, i32)
337-
spirv.BranchConditional %true, ^true1(%one: i32), ^false1(%zero, %zero: i32, i32)
365+
spirv.BranchConditional %true, ^true1(%one: i32), ^false1(%zero, %zero: i32, i32)
338366
// CHECK: [[true1]](%{{.*}}: i32):
339-
^true1(%arg0: i32):
340-
spirv.Return
367+
^true1(%arg0: i32):
368+
spirv.Return
341369
// CHECK: [[false1]](%{{.*}}: i32, %{{.*}}: i32):
342-
^false1(%arg1: i32, %arg2: i32):
370+
^false1(%arg1: i32, %arg2: i32):
371+
spirv.Return
372+
^merge:
373+
spirv.mlir.merge
374+
}
375+
343376
spirv.Return
344377
}
378+
379+
spirv.func @main() -> () "None" {
380+
spirv.Return
381+
}
382+
spirv.EntryPoint "GLCompute" @main
345383
}

mlir/test/Target/SPIRV/selection.mlir

Lines changed: 21 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,10 @@
11
// RUN: mlir-translate -no-implicit-module -test-spirv-roundtrip -split-input-file %s | FileCheck %s
22

3+
// RUN: %if spirv-tools %{ rm -rf %t %}
4+
// RUN: %if spirv-tools %{ mkdir %t %}
5+
// RUN: %if spirv-tools %{ mlir-translate --no-implicit-module --serialize-spirv --split-input-file --spirv-save-validation-files-with-prefix=%t/module %s %}
6+
// RUN: %if spirv-tools %{ spirv-val %t %}
7+
38
// Selection with both then and else branches
49

510
spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], []> {
@@ -136,19 +141,31 @@ spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader], []> {
136141

137142
// CHECK-NEXT: spirv.Load "Function" %[[VAR]]
138143
%cond = spirv.Load "Function" %var : i1
144+
spirv.mlir.selection {
139145
// CHECK: spirv.BranchConditional %1, ^[[THEN1:.+]](%{{.+}} : i32), ^[[ELSE1:.+]](%{{.+}}, %{{.+}} : i32, i32)
140-
spirv.BranchConditional %cond, ^then1(%one: i32), ^else1(%zero, %zero: i32, i32)
146+
spirv.BranchConditional %cond, ^then1(%one: i32), ^else1(%zero, %zero: i32, i32)
141147

142148
// CHECK-NEXT: ^[[THEN1]](%{{.+}}: i32):
143149
// CHECK-NEXT: spirv.Return
144-
^then1(%arg0: i32):
145-
spirv.Return
150+
^then1(%arg0: i32):
151+
spirv.Return
146152

147153
// CHECK-NEXT: ^[[ELSE1]](%{{.+}}: i32, %{{.+}}: i32):
148154
// CHECK-NEXT: spirv.Return
149-
^else1(%arg1: i32, %arg2: i32):
155+
^else1(%arg1: i32, %arg2: i32):
156+
spirv.Return
157+
^merge:
158+
spirv.mlir.merge
159+
}
160+
150161
spirv.Return
151162
}
163+
164+
spirv.func @main() -> () "None" {
165+
spirv.Return
166+
}
167+
spirv.EntryPoint "GLCompute" @main
168+
spirv.ExecutionMode @main "LocalSize", 1, 1, 1
152169
}
153170

154171
// -----

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