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[AMDGPU] Regenerate test checks for mad24 tests (#162455)
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‎llvm/test/CodeGen/AMDGPU/mad_int24.ll‎

Lines changed: 281 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,79 @@
1-
; RUN: llc < %s -mtriple=amdgcn | FileCheck %s --check-prefix=GCN --check-prefix=FUNC
2-
; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck %s --check-prefix=GCN --check-prefix=FUNC
3-
; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
4-
; RUN: llc < %s -mtriple=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+
; RUN: llc < %s -mtriple=amdgcn| FileCheck %s --check-prefixes=GCN
3+
; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck %s --check-prefixes=VI
4+
; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s --check-prefixes=EG,R600,RW
5+
; RUN: llc < %s -mtriple=r600 -mcpu=cayman | FileCheck %s --check-prefixes=EG,R600,CM
56

6-
; FUNC-LABEL: {{^}}i32_mad24:
77
; Signed 24-bit multiply is not supported on pre-Cayman GPUs.
8-
; EG: MULLO_INT
9-
; CM: MULLO_INT
10-
; GCN: s_bfe_i32
11-
; GCN: s_bfe_i32
12-
; GCN: s_mul_i32
13-
; GCN: s_add_i32
148
define amdgpu_kernel void @i32_mad24(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {
9+
; GCN-LABEL: i32_mad24:
10+
; GCN: ; %bb.0: ; %entry
11+
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
12+
; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
13+
; GCN-NEXT: s_mov_b32 s7, 0xf000
14+
; GCN-NEXT: s_waitcnt lgkmcnt(0)
15+
; GCN-NEXT: s_bfe_i32 s0, s0, 0x180000
16+
; GCN-NEXT: s_bfe_i32 s1, s1, 0x180000
17+
; GCN-NEXT: s_mul_i32 s0, s0, s1
18+
; GCN-NEXT: s_add_i32 s0, s0, s2
19+
; GCN-NEXT: s_mov_b32 s6, -1
20+
; GCN-NEXT: v_mov_b32_e32 v0, s0
21+
; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
22+
; GCN-NEXT: s_endpgm
23+
;
24+
; VI-LABEL: i32_mad24:
25+
; VI: ; %bb.0: ; %entry
26+
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
27+
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
28+
; VI-NEXT: s_mov_b32 s7, 0xf000
29+
; VI-NEXT: s_mov_b32 s6, -1
30+
; VI-NEXT: s_waitcnt lgkmcnt(0)
31+
; VI-NEXT: s_bfe_i32 s0, s0, 0x180000
32+
; VI-NEXT: s_bfe_i32 s1, s1, 0x180000
33+
; VI-NEXT: s_mul_i32 s0, s0, s1
34+
; VI-NEXT: s_add_i32 s0, s0, s2
35+
; VI-NEXT: v_mov_b32_e32 v0, s0
36+
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
37+
; VI-NEXT: s_endpgm
38+
;
39+
; RW-LABEL: i32_mad24:
40+
; RW: ; %bb.0: ; %entry
41+
; RW-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
42+
; RW-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
43+
; RW-NEXT: CF_END
44+
; RW-NEXT: PAD
45+
; RW-NEXT: ALU clause starting at 4:
46+
; RW-NEXT: LSHL T0.W, KC0[2].Z, literal.x,
47+
; RW-NEXT: LSHL * T1.W, KC0[2].W, literal.x,
48+
; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)
49+
; RW-NEXT: ASHR T1.W, PS, literal.x,
50+
; RW-NEXT: ASHR * T0.W, PV.W, literal.x,
51+
; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)
52+
; RW-NEXT: MULLO_INT * T0.X, PS, PV.W,
53+
; RW-NEXT: ADD_INT T0.X, PS, KC0[3].X,
54+
; RW-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
55+
; RW-NEXT: 2(2.802597e-45), 0(0.000000e+00)
56+
;
57+
; CM-LABEL: i32_mad24:
58+
; CM: ; %bb.0: ; %entry
59+
; CM-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]
60+
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
61+
; CM-NEXT: CF_END
62+
; CM-NEXT: PAD
63+
; CM-NEXT: ALU clause starting at 4:
64+
; CM-NEXT: LSHL T0.Z, KC0[2].Z, literal.x,
65+
; CM-NEXT: LSHL * T0.W, KC0[2].W, literal.x,
66+
; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
67+
; CM-NEXT: ASHR T1.Z, PV.W, literal.x,
68+
; CM-NEXT: ASHR * T0.W, PV.Z, literal.x,
69+
; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
70+
; CM-NEXT: MULLO_INT T0.X, T0.W, T1.Z,
71+
; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T1.Z,
72+
; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T1.Z,
73+
; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T1.Z,
74+
; CM-NEXT: ADD_INT * T0.X, PV.X, KC0[3].X,
75+
; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
76+
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1577
entry:
1678
%0 = shl i32 %a, 8
1779
%a_24 = ashr i32 %0, 8
@@ -23,13 +85,25 @@ entry:
2385
ret void
2486
}
2587

26-
; GCN-LABEL: {{^}}mad24_known_bits_destroyed:
27-
; GCN: s_waitcnt
28-
; GCN-NEXT: v_mad_i32_i24
29-
; GCN-NEXT: v_mul_i32_i24
30-
; GCN-NEXT: s_setpc_b64
3188
define i32 @mad24_known_bits_destroyed(i32 %a, i32 %b, i32 %c) {
32-
89+
; GCN-LABEL: mad24_known_bits_destroyed:
90+
; GCN: ; %bb.0:
91+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
92+
; GCN-NEXT: v_mad_i32_i24 v1, v0, v1, v2
93+
; GCN-NEXT: v_mul_i32_i24_e32 v0, v1, v0
94+
; GCN-NEXT: s_setpc_b64 s[30:31]
95+
;
96+
; VI-LABEL: mad24_known_bits_destroyed:
97+
; VI: ; %bb.0:
98+
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
99+
; VI-NEXT: v_mad_i32_i24 v1, v0, v1, v2
100+
; VI-NEXT: v_mul_i32_i24_e32 v0, v1, v0
101+
; VI-NEXT: s_setpc_b64 s[30:31]
102+
;
103+
; EG-LABEL: mad24_known_bits_destroyed:
104+
; EG: ; %bb.0:
105+
; EG-NEXT: CF_END
106+
; EG-NEXT: PAD
33107
%shl.0 = shl i32 %a, 8
34108
%sra.0 = ashr i32 %shl.0, 8
35109
%shl.1 = shl i32 %b, 8
@@ -48,12 +122,25 @@ define i32 @mad24_known_bits_destroyed(i32 %a, i32 %b, i32 %c) {
48122
ret i32 %mul1
49123
}
50124

51-
; GCN-LABEL: {{^}}mad24_intrin_known_bits_destroyed:
52-
; GCN: s_waitcnt
53-
; GCN-NEXT: v_mad_i32_i24
54-
; GCN-NEXT: v_mul_i32_i24
55-
; GCN-NEXT: s_setpc_b64
56125
define i32 @mad24_intrin_known_bits_destroyed(i32 %a, i32 %b, i32 %c) {
126+
; GCN-LABEL: mad24_intrin_known_bits_destroyed:
127+
; GCN: ; %bb.0:
128+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
129+
; GCN-NEXT: v_mad_i32_i24 v1, v0, v1, v2
130+
; GCN-NEXT: v_mul_i32_i24_e32 v0, v1, v0
131+
; GCN-NEXT: s_setpc_b64 s[30:31]
132+
;
133+
; VI-LABEL: mad24_intrin_known_bits_destroyed:
134+
; VI: ; %bb.0:
135+
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
136+
; VI-NEXT: v_mad_i32_i24 v1, v0, v1, v2
137+
; VI-NEXT: v_mul_i32_i24_e32 v0, v1, v0
138+
; VI-NEXT: s_setpc_b64 s[30:31]
139+
;
140+
; EG-LABEL: mad24_intrin_known_bits_destroyed:
141+
; EG: ; %bb.0:
142+
; EG-NEXT: CF_END
143+
; EG-NEXT: PAD
57144
%shl.0 = shl i32 %a, 8
58145
%sra.0 = ashr i32 %shl.0, 8
59146
%shl.1 = shl i32 %b, 8
@@ -73,17 +160,177 @@ define i32 @mad24_intrin_known_bits_destroyed(i32 %a, i32 %b, i32 %c) {
73160
}
74161

75162
; Make sure no unnecessary BFEs are emitted in the loop.
76-
; GCN-LABEL: {{^}}mad24_destroyed_knownbits_2:
77-
; GCN-NOT: v_bfe
78-
; GCN: v_mad_i32_i24
79-
; GCN-NOT: v_bfe
80-
; GCN: v_mad_i32_i24
81-
; GCN-NOT: v_bfe
82-
; GCN: v_mad_i32_i24
83-
; GCN-NOT: v_bfe
84-
; GCN: v_mad_i32_i24
85-
; GCN-NOT: v_bfe
86163
define void @mad24_destroyed_knownbits_2(i32 %arg, i32 %arg1, i32 %arg2, ptr addrspace(1) %arg3) {
164+
; GCN-LABEL: mad24_destroyed_knownbits_2:
165+
; GCN: ; %bb.0: ; %bb
166+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
167+
; GCN-NEXT: v_mov_b32_e32 v5, 1
168+
; GCN-NEXT: s_mov_b64 s[4:5], 0
169+
; GCN-NEXT: .LBB3_1: ; %bb6
170+
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
171+
; GCN-NEXT: v_mad_i32_i24 v0, v0, v5, v5
172+
; GCN-NEXT: v_add_i32_e32 v1, vcc, -1, v1
173+
; GCN-NEXT: v_mad_i32_i24 v5, v0, v5, v0
174+
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
175+
; GCN-NEXT: v_mad_i32_i24 v0, v5, v0, v5
176+
; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
177+
; GCN-NEXT: v_mad_i32_i24 v0, v0, v5, v0
178+
; GCN-NEXT: v_mov_b32_e32 v5, v2
179+
; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5]
180+
; GCN-NEXT: s_cbranch_execnz .LBB3_1
181+
; GCN-NEXT: ; %bb.2: ; %bb5
182+
; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
183+
; GCN-NEXT: s_mov_b32 s6, 0
184+
; GCN-NEXT: s_mov_b32 s7, 0xf000
185+
; GCN-NEXT: s_mov_b32 s4, s6
186+
; GCN-NEXT: s_mov_b32 s5, s6
187+
; GCN-NEXT: buffer_store_dword v0, v[3:4], s[4:7], 0 addr64
188+
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
189+
; GCN-NEXT: s_setpc_b64 s[30:31]
190+
;
191+
; VI-LABEL: mad24_destroyed_knownbits_2:
192+
; VI: ; %bb.0: ; %bb
193+
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
194+
; VI-NEXT: v_mov_b32_e32 v5, 1
195+
; VI-NEXT: s_mov_b64 s[4:5], 0
196+
; VI-NEXT: .LBB3_1: ; %bb6
197+
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
198+
; VI-NEXT: v_mad_i32_i24 v0, v0, v5, v5
199+
; VI-NEXT: v_mad_i32_i24 v5, v0, v5, v0
200+
; VI-NEXT: v_add_u32_e32 v1, vcc, -1, v1
201+
; VI-NEXT: v_mad_i32_i24 v0, v5, v0, v5
202+
; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
203+
; VI-NEXT: v_mad_i32_i24 v0, v0, v5, v0
204+
; VI-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
205+
; VI-NEXT: v_mov_b32_e32 v5, v2
206+
; VI-NEXT: s_andn2_b64 exec, exec, s[4:5]
207+
; VI-NEXT: s_cbranch_execnz .LBB3_1
208+
; VI-NEXT: ; %bb.2: ; %bb5
209+
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
210+
; VI-NEXT: flat_store_dword v[3:4], v0
211+
; VI-NEXT: s_waitcnt vmcnt(0)
212+
; VI-NEXT: s_setpc_b64 s[30:31]
213+
;
214+
; RW-LABEL: mad24_destroyed_knownbits_2:
215+
; RW: ; %bb.0: ; %bb
216+
; RW-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[]
217+
; RW-NEXT: LOOP_START_DX10 @7
218+
; RW-NEXT: ALU_PUSH_BEFORE 30, @16, KC0[], KC1[]
219+
; RW-NEXT: JUMP @6 POP:1
220+
; RW-NEXT: LOOP_BREAK @6
221+
; RW-NEXT: POP @6 POP:1
222+
; RW-NEXT: END_LOOP @2
223+
; RW-NEXT: ALU 1, @47, KC0[], KC1[]
224+
; RW-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
225+
; RW-NEXT: CF_END
226+
; RW-NEXT: ALU clause starting at 10:
227+
; RW-NEXT: MOV T0.X, KC0[2].Y,
228+
; RW-NEXT: MOV T0.Y, KC0[2].Z,
229+
; RW-NEXT: MOV * T0.Z, KC0[2].W,
230+
; RW-NEXT: MOV T0.W, KC0[3].X,
231+
; RW-NEXT: MOV * T1.W, literal.x,
232+
; RW-NEXT: 1(1.401298e-45), 0(0.000000e+00)
233+
; RW-NEXT: ALU clause starting at 16:
234+
; RW-NEXT: LSHL T2.W, T1.W, literal.x,
235+
; RW-NEXT: LSHL * T3.W, T0.X, literal.x,
236+
; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)
237+
; RW-NEXT: ASHR T3.W, PS, literal.x,
238+
; RW-NEXT: ASHR * T2.W, PV.W, literal.x,
239+
; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)
240+
; RW-NEXT: MULLO_INT * T0.X, PV.W, PS,
241+
; RW-NEXT: ADD_INT * T1.W, PS, T1.W,
242+
; RW-NEXT: LSHL * T3.W, PV.W, literal.x,
243+
; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)
244+
; RW-NEXT: ASHR * T3.W, PV.W, literal.x,
245+
; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)
246+
; RW-NEXT: MULLO_INT * T0.X, PV.W, T2.W,
247+
; RW-NEXT: ADD_INT * T1.W, PS, T1.W,
248+
; RW-NEXT: LSHL * T2.W, PV.W, literal.x,
249+
; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)
250+
; RW-NEXT: ASHR * T2.W, PV.W, literal.x,
251+
; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)
252+
; RW-NEXT: MULLO_INT * T0.X, PV.W, T3.W,
253+
; RW-NEXT: ADD_INT * T1.W, PS, T1.W,
254+
; RW-NEXT: LSHL * T3.W, PV.W, literal.x,
255+
; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)
256+
; RW-NEXT: ASHR * T3.W, PV.W, literal.x,
257+
; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)
258+
; RW-NEXT: ADD_INT T0.Y, T0.Y, literal.x,
259+
; RW-NEXT: MULLO_INT * T0.X, PV.W, T2.W,
260+
; RW-NEXT: -1(nan), 0(0.000000e+00)
261+
; RW-NEXT: ADD_INT T0.X, PS, T1.W,
262+
; RW-NEXT: SETE_INT T2.W, PV.Y, 0.0,
263+
; RW-NEXT: MOV * T1.W, T0.Z,
264+
; RW-NEXT: PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0,
265+
; RW-NEXT: ALU clause starting at 47:
266+
; RW-NEXT: LSHR * T1.X, T0.W, literal.x,
267+
; RW-NEXT: 2(2.802597e-45), 0(0.000000e+00)
268+
;
269+
; CM-LABEL: mad24_destroyed_knownbits_2:
270+
; CM: ; %bb.0: ; %bb
271+
; CM-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[]
272+
; CM-NEXT: LOOP_START_DX10 @7
273+
; CM-NEXT: ALU_PUSH_BEFORE 41, @16, KC0[], KC1[]
274+
; CM-NEXT: JUMP @6 POP:1
275+
; CM-NEXT: LOOP_BREAK @6
276+
; CM-NEXT: POP @6 POP:1
277+
; CM-NEXT: END_LOOP @2
278+
; CM-NEXT: ALU 1, @58, KC0[], KC1[]
279+
; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
280+
; CM-NEXT: CF_END
281+
; CM-NEXT: ALU clause starting at 10:
282+
; CM-NEXT: MOV * T1.X, KC0[2].Y,
283+
; CM-NEXT: MOV T0.X, KC0[2].Z,
284+
; CM-NEXT: MOV T0.Y, KC0[2].W,
285+
; CM-NEXT: MOV T0.Z, KC0[3].X,
286+
; CM-NEXT: MOV * T0.W, literal.x,
287+
; CM-NEXT: 1(1.401298e-45), 0(0.000000e+00)
288+
; CM-NEXT: ALU clause starting at 16:
289+
; CM-NEXT: LSHL T1.Z, T0.W, literal.x,
290+
; CM-NEXT: LSHL * T1.W, T1.X, literal.x,
291+
; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
292+
; CM-NEXT: ASHR T2.Z, PV.W, literal.x,
293+
; CM-NEXT: ASHR * T1.W, PV.Z, literal.x,
294+
; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
295+
; CM-NEXT: MULLO_INT T1.X, T2.Z, T1.W,
296+
; CM-NEXT: MULLO_INT T1.Y (MASKED), T2.Z, T1.W,
297+
; CM-NEXT: MULLO_INT T1.Z (MASKED), T2.Z, T1.W,
298+
; CM-NEXT: MULLO_INT * T1.W (MASKED), T2.Z, T1.W,
299+
; CM-NEXT: ADD_INT * T0.W, PV.X, T0.W,
300+
; CM-NEXT: LSHL * T2.W, PV.W, literal.x,
301+
; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
302+
; CM-NEXT: ASHR * T2.W, PV.W, literal.x,
303+
; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
304+
; CM-NEXT: MULLO_INT T1.X, T2.W, T1.W,
305+
; CM-NEXT: MULLO_INT T1.Y (MASKED), T2.W, T1.W,
306+
; CM-NEXT: MULLO_INT T1.Z (MASKED), T2.W, T1.W,
307+
; CM-NEXT: MULLO_INT * T1.W (MASKED), T2.W, T1.W,
308+
; CM-NEXT: ADD_INT * T0.W, PV.X, T0.W,
309+
; CM-NEXT: LSHL * T1.W, PV.W, literal.x,
310+
; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
311+
; CM-NEXT: ASHR * T1.W, PV.W, literal.x,
312+
; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
313+
; CM-NEXT: MULLO_INT T1.X, T1.W, T2.W,
314+
; CM-NEXT: MULLO_INT T1.Y (MASKED), T1.W, T2.W,
315+
; CM-NEXT: MULLO_INT T1.Z (MASKED), T1.W, T2.W,
316+
; CM-NEXT: MULLO_INT * T1.W (MASKED), T1.W, T2.W,
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; CM-NEXT: ADD_INT * T0.W, PV.X, T0.W,
318+
; CM-NEXT: LSHL * T2.W, PV.W, literal.x,
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; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
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; CM-NEXT: ADD_INT T0.X, T0.X, literal.x,
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; CM-NEXT: ASHR * T2.W, PV.W, literal.y,
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; CM-NEXT: -1(nan), 8(1.121039e-44)
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; CM-NEXT: MULLO_INT T1.X, T2.W, T1.W,
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; CM-NEXT: MULLO_INT T1.Y (MASKED), T2.W, T1.W,
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; CM-NEXT: MULLO_INT T1.Z (MASKED), T2.W, T1.W,
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; CM-NEXT: MULLO_INT * T1.W (MASKED), T2.W, T1.W,
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; CM-NEXT: ADD_INT T1.X, PV.X, T0.W,
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; CM-NEXT: SETE_INT T1.Z, T0.X, 0.0,
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; CM-NEXT: MOV * T0.W, T0.Y,
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; CM-NEXT: PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.Z, 0.0,
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; CM-NEXT: ALU clause starting at 58:
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; CM-NEXT: LSHR * T0.X, T0.Z, literal.x,
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; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
87334
bb:
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br label %bb6
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@@ -119,3 +366,5 @@ bb6: ; preds = %bb6, %bb
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}
120367

121368
declare i32 @llvm.amdgcn.mul.i24(i32, i32)
369+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; R600: {{.*}}

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