Wrap OpDPdx/yCoarse with OpFConvert where needed.

HLSL allows half types as arg and result to dd/y_coarse. This is not
allowed in SPIRV, so to manage this we must detect these cases and wrap
the OpDPd instructions in OpFConvert from half -> float -> half.

Author: Alexander Johnston

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

@@ -325,6 +325,8 @@ class SPIRVInstructionSelector : public InstructionSelector {
                            MachineInstr &I) const;
   bool selectFrexp(Register ResVReg, const SPIRVType *ResType,
                    MachineInstr &I) const;
+  bool selectDpdCoarse(Register ResVReg, const SPIRVType *ResType,
+                       MachineInstr &I, const unsigned DPdOpCode) const;
   // Utilities
   std::pair<Register, bool>
   buildI32Constant(uint32_t Val, MachineInstr &I,
@@ -3099,6 +3101,59 @@ bool SPIRVInstructionSelector::wrapIntoSpecConstantOp(
   return Result;
 }
 
+bool SPIRVInstructionSelector::selectDpdCoarse(Register ResVReg,
+                                               const SPIRVType *ResType,
+                                               MachineInstr &I,
+                                               const unsigned DPdOpCode) const {
+  // If the arg/result types are half then we need to wrap the instr in
+  // conversions to float
+  // This case occurs because a half arg/result is legal in HLSL but not spirv.
+  Register SrcReg = I.getOperand(2).getReg();
+  SPIRVType *SrcType = GR.getSPIRVTypeForVReg(SrcReg);
+  unsigned BitWidth = std::min(GR.getScalarOrVectorBitWidth(SrcType),
+                               GR.getScalarOrVectorBitWidth(ResType));
+  if (BitWidth == 32) {
+    return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DPdOpCode))
+        .addDef(ResVReg)
+        .addUse(GR.getSPIRVTypeID(ResType))
+        .addUse(I.getOperand(2).getReg());
+  } else {
+    MachineIRBuilder MIRBuilder(I);
+    unsigned componentCount = GR.getScalarOrVectorComponentCount(SrcType);
+    SPIRVType *Float32Ty = GR.getOrCreateSPIRVFloatType(32, I, TII);
+    SPIRVType *F32ConvertTy;
+    if (componentCount == 1) {
+      F32ConvertTy = Float32Ty;
+    } else {
+      F32ConvertTy = GR.getOrCreateSPIRVVectorType(Float32Ty, componentCount,
+                                                   MIRBuilder, false);
+    }
+
+    const TargetRegisterClass *RegClass = GR.getRegClass(SrcType);
+    Register ConvertToVReg = MRI->createVirtualRegister(RegClass);
+    Register DpdOpVReg = MRI->createVirtualRegister(RegClass);
+
+    bool Result =
+        BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert))
+            .addDef(ConvertToVReg)
+            .addUse(GR.getSPIRVTypeID(F32ConvertTy))
+            .addUse(SrcReg)
+            .constrainAllUses(TII, TRI, RBI);
+    Result &= BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DPdOpCode))
+                  .addDef(DpdOpVReg)
+                  .addUse(GR.getSPIRVTypeID(F32ConvertTy))
+                  .addUse(ConvertToVReg)
+                  .constrainAllUses(TII, TRI, RBI);
+    Result &=
+        BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert))
+            .addDef(ResVReg)
+            .addUse(GR.getSPIRVTypeID(ResType))
+            .addUse(DpdOpVReg)
+            .constrainAllUses(TII, TRI, RBI);
+    return Result;
+  }
+}
+
 bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
                                                const SPIRVType *ResType,
                                                MachineInstr &I) const {
@@ -3473,18 +3528,10 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
     return selectResourceNonUniformIndex(ResVReg, ResType, I);
   }
   case Intrinsic::spv_ddx_coarse: {
-    return BuildMI(*I.getParent(), I, I.getDebugLoc(),
-                   TII.get(SPIRV::OpDPdxCoarse))
-        .addDef(ResVReg)
-        .addUse(GR.getSPIRVTypeID(ResType))
-        .addUse(I.getOperand(2).getReg());
+    return selectDpdCoarse(ResVReg, ResType, I, SPIRV::OpDPdxCoarse);
   }
   case Intrinsic::spv_ddy_coarse: {
-    return BuildMI(*I.getParent(), I, I.getDebugLoc(),
-                   TII.get(SPIRV::OpDPdyCoarse))
-        .addDef(ResVReg)
-        .addUse(GR.getSPIRVTypeID(ResType))
-        .addUse(I.getOperand(2).getReg());
+    return selectDpdCoarse(ResVReg, ResType, I, SPIRV::OpDPdyCoarse);
   }
   default: {
     std::string DiagMsg;

llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp

@@ -934,7 +934,8 @@ void RequirementHandler::initAvailableCapabilitiesForVulkan(
                     Capability::UniformBufferArrayDynamicIndexing,
                     Capability::SampledImageArrayDynamicIndexing,
                     Capability::StorageBufferArrayDynamicIndexing,
-                    Capability::StorageImageArrayDynamicIndexing});
+                    Capability::StorageImageArrayDynamicIndexing,
+                    Capability::DerivativeControl});
 
   // Became core in Vulkan 1.2
   if (ST.isAtLeastSPIRVVer(VersionTuple(1, 5))) {
@@ -2061,6 +2062,11 @@ void addInstrRequirements(const MachineInstr &MI,
     Reqs.addCapability(SPIRV::Capability::PredicatedIOINTEL);
     break;
   }
+  case SPIRV::OpDPdxCoarse:
+  case SPIRV::OpDPdyCoarse: {
+    Reqs.addCapability(SPIRV::Capability::DerivativeControl);
+    break;
+  }
 
   default:
     break;

llvm/test/CodeGen/SPIRV/hlsl-intrinsics/ddx_coarse.ll

@@ -18,7 +18,9 @@ entry:
 define noundef half @ddx_coarse_half(half noundef %a) {
 entry:
 ; CHECK: %[[#float_16_arg:]] = OpFunctionParameter %[[#float_16]]
-; CHECK: %[[#]] = OpDPdxCoarse %[[#float_16]] %[[#float_16_arg]]
+; CHECK: %[[#converted:]] = OpFConvert %[[#float_32:]] %[[#float_16_arg]]
+; CHECK: %[[#coarse:]] = OpDPdxCoarse %[[#float_32]] %[[#converted]]
+; CHECK: %[[#]] = OpFConvert %[[#float_16]] %[[#coarse]]
   %elt.ddx.coarse = call half @llvm.spv.ddx.coarse.f16(half %a)
   ret half %elt.ddx.coarse
 }
@@ -34,7 +36,9 @@ entry:
 define noundef <4 x half> @ddx_coarse_half_vector(<4 x half> noundef %a) {
 entry:
 ; CHECK: %[[#vec4_float_16_arg:]] = OpFunctionParameter %[[#vec4_float_16]]
-; CHECK: %[[#]] = OpDPdxCoarse %[[#vec4_float_16]] %[[#vec4_float_16_arg]]
+; CHECK: %[[#converted:]] = OpFConvert %[[#vec4_float_32:]] %[[#vec4_float_16_arg]]
+; CHECK: %[[#coarse:]] = OpDPdxCoarse %[[#vec4_float_32]] %[[#converted]]
+; CHECK: %[[#]] = OpFConvert %[[#vec4_float_16]] %[[#coarse]]
   %elt.ddx.coarse = call <4 x half> @llvm.spv.ddx.coarse.v4f16(<4 x half> %a)
   ret <4 x half> %elt.ddx.coarse
 }

llvm/test/CodeGen/SPIRV/hlsl-intrinsics/ddy_coarse.ll

@@ -18,7 +18,9 @@ entry:
 define noundef half @ddy_coarse_half(half noundef %a) {
 entry:
 ; CHECK: %[[#float_16_arg:]] = OpFunctionParameter %[[#float_16]]
-; CHECK: %[[#]] = OpDPdyCoarse %[[#float_16]] %[[#float_16_arg]]
+; CHECK: %[[#converted:]] = OpFConvert %[[#float_32:]] %[[#float_16_arg]]
+; CHECK: %[[#coarse:]] = OpDPdyCoarse %[[#float_32]] %[[#converted]]
+; CHECK: %[[#]] = OpFConvert %[[#float_16]] %[[#coarse]]
   %elt.ddy.coarse = call half @llvm.spv.ddy.coarse.f16(half %a)
   ret half %elt.ddy.coarse
 }
@@ -34,7 +36,9 @@ entry:
 define noundef <4 x half> @ddy_coarse_half_vector(<4 x half> noundef %a) {
 entry:
 ; CHECK: %[[#vec4_float_16_arg:]] = OpFunctionParameter %[[#vec4_float_16]]
-; CHECK: %[[#]] = OpDPdyCoarse %[[#vec4_float_16]] %[[#vec4_float_16_arg]]
+; CHECK: %[[#converted:]] = OpFConvert %[[#vec4_float_32:]] %[[#vec4_float_16_arg]]
+; CHECK: %[[#coarse:]] = OpDPdyCoarse %[[#vec4_float_32]] %[[#converted]]
+; CHECK: %[[#]] = OpFConvert %[[#vec4_float_16]] %[[#coarse]]
   %elt.ddy.coarse = call <4 x half> @llvm.spv.ddy.coarse.v4f16(<4 x half> %a)
   ret <4 x half> %elt.ddy.coarse
 }