Skip to content

Commit a28208f

Browse files
arsenmarsenm
committed
CodeGen: Remove TRI argument from reMaterialize
1 parent 37b57b5 commit a28208f

File tree

11 files changed

+17
-24
lines changed

11 files changed

+17
-24
lines changed

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -461,8 +461,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
461461
/// SubIdx.
462462
virtual void reMaterialize(MachineBasicBlock &MBB,
463463
MachineBasicBlock::iterator MI, Register DestReg,
464-
unsigned SubIdx, const MachineInstr &Orig,
465-
const TargetRegisterInfo &TRI) const;
464+
unsigned SubIdx, const MachineInstr &Orig) const;
466465

467466
/// Clones instruction or the whole instruction bundle \p Orig and
468467
/// insert into \p MBB before \p InsertBefore. The target may update operands

‎llvm/lib/CodeGen/LiveRangeEdit.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -88,7 +88,7 @@ SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
8888
bool Late, unsigned SubIdx,
8989
MachineInstr *ReplaceIndexMI) {
9090
assert(RM.OrigMI && "Invalid remat");
91-
TII.reMaterialize(MBB, MI, DestReg, SubIdx, *RM.OrigMI, tri);
91+
TII.reMaterialize(MBB, MI, DestReg, SubIdx, *RM.OrigMI);
9292
// DestReg of the cloned instruction cannot be Dead. Set isDead of DestReg
9393
// to false anyway in case the isDead flag of RM.OrigMI's dest register
9494
// is true.

‎llvm/lib/CodeGen/MachineSink.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -569,7 +569,7 @@ bool MachineSinking::PerformSinkAndFold(MachineInstr &MI,
569569
// Sink a copy of the instruction, replacing a COPY instruction.
570570
MachineBasicBlock::iterator InsertPt = SinkDst->getIterator();
571571
Register DstReg = SinkDst->getOperand(0).getReg();
572-
TII->reMaterialize(*SinkDst->getParent(), InsertPt, DstReg, 0, MI, *TRI);
572+
TII->reMaterialize(*SinkDst->getParent(), InsertPt, DstReg, 0, MI);
573573
New = &*std::prev(InsertPt);
574574
if (!New->getDebugLoc())
575575
New->setDebugLoc(SinkDst->getDebugLoc());

‎llvm/lib/CodeGen/TargetInstrInfo.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -448,10 +448,10 @@ bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
448448
return true;
449449
}
450450

451-
void TargetInstrInfo::reMaterialize(
452-
MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
453-
unsigned SubIdx, const MachineInstr &Orig,
454-
const TargetRegisterInfo & /*Remove me*/) const {
451+
void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
452+
MachineBasicBlock::iterator I,
453+
Register DestReg, unsigned SubIdx,
454+
const MachineInstr &Orig) const {
455455
MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
456456
MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
457457
MBB.insert(I, MI);

‎llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2011,7 +2011,7 @@ void PreRARematStage::rematerialize() {
20112011

20122012
// Rematerialize DefMI to its use block.
20132013
TII->reMaterialize(*InsertPos->getParent(), InsertPos, Reg,
2014-
AMDGPU::NoSubRegister, *DefMI, *DAG.TRI);
2014+
AMDGPU::NoSubRegister, *DefMI);
20152015
Remat.RematMI = &*std::prev(InsertPos);
20162016
DAG.LIS->InsertMachineInstrInMaps(*Remat.RematMI);
20172017

@@ -2163,8 +2163,7 @@ void PreRARematStage::finalizeGCNSchedStage() {
21632163
// Re-rematerialize MI at the end of its original region. Note that it may
21642164
// not be rematerialized exactly in the same position as originally within
21652165
// the region, but it should not matter much.
2166-
TII->reMaterialize(*MBB, InsertPos, Reg, AMDGPU::NoSubRegister, RematMI,
2167-
*DAG.TRI);
2166+
TII->reMaterialize(*MBB, InsertPos, Reg, AMDGPU::NoSubRegister, RematMI);
21682167
MachineInstr *NewMI = &*std::prev(InsertPos);
21692168
DAG.LIS->InsertMachineInstrInMaps(*NewMI);
21702169

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2519,8 +2519,8 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
25192519

25202520
void SIInstrInfo::reMaterialize(MachineBasicBlock &MBB,
25212521
MachineBasicBlock::iterator I, Register DestReg,
2522-
unsigned SubIdx, const MachineInstr &Orig,
2523-
const TargetRegisterInfo &RI) const {
2522+
unsigned SubIdx,
2523+
const MachineInstr &Orig) const {
25242524

25252525
// Try shrinking the instruction to remat only the part needed for current
25262526
// context.
@@ -2600,7 +2600,7 @@ void SIInstrInfo::reMaterialize(MachineBasicBlock &MBB,
26002600
break;
26012601
}
26022602

2603-
TargetInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig, RI);
2603+
TargetInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig);
26042604
}
26052605

26062606
std::pair<MachineInstr*, MachineInstr*>

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -321,8 +321,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
321321

322322
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
323323
Register DestReg, unsigned SubIdx,
324-
const MachineInstr &Orig,
325-
const TargetRegisterInfo &TRI) const override;
324+
const MachineInstr &Orig) const override;
326325

327326
// Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
328327
// instructions. Returns a pair of generated instructions.

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1653,8 +1653,7 @@ static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
16531653
void ARMBaseInstrInfo::reMaterialize(MachineBasicBlock &MBB,
16541654
MachineBasicBlock::iterator I,
16551655
Register DestReg, unsigned SubIdx,
1656-
const MachineInstr &Orig,
1657-
const TargetRegisterInfo &TRI) const {
1656+
const MachineInstr &Orig) const {
16581657
unsigned Opcode = Orig.getOpcode();
16591658
switch (Opcode) {
16601659
default: {

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.h‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -232,8 +232,7 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
232232

233233
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
234234
Register DestReg, unsigned SubIdx,
235-
const MachineInstr &Orig,
236-
const TargetRegisterInfo &TRI) const override;
235+
const MachineInstr &Orig) const override;
237236

238237
MachineInstr &
239238
duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,

‎llvm/lib/Target/X86/X86InstrInfo.cpp‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -958,8 +958,7 @@ bool X86InstrInfo::isReMaterializableImpl(
958958
void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
959959
MachineBasicBlock::iterator I,
960960
Register DestReg, unsigned SubIdx,
961-
const MachineInstr &Orig,
962-
const TargetRegisterInfo &TRI) const {
961+
const MachineInstr &Orig) const {
963962
bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
964963
if (ClobbersEFLAGS && MBB.computeRegisterLiveness(&TRI, X86::EFLAGS, I) !=
965964
MachineBasicBlock::LQR_Dead) {

0 commit comments

Comments
 (0)