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CodeGen: Remove TRI arguments from stack load/store hooks
This is directly available in TargetInstrInfo
1 parent 02ecbf5 commit c138ffb

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63 files changed

+316
-347
lines changed

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1165,8 +1165,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
11651165
/// register spill instruction, part of prologue, during the frame lowering.
11661166
virtual void storeRegToStackSlot(
11671167
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
1168-
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
1169-
const TargetRegisterInfo *TRI, Register VReg,
1168+
bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
11701169
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const {
11711170
llvm_unreachable("Target didn't implement "
11721171
"TargetInstrInfo::storeRegToStackSlot!");
@@ -1184,8 +1183,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
11841183
/// register reload instruction, part of epilogue, during the frame lowering.
11851184
virtual void loadRegFromStackSlot(
11861185
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
1187-
int FrameIndex, const TargetRegisterClass *RC,
1188-
const TargetRegisterInfo *TRI, Register VReg,
1186+
int FrameIndex, const TargetRegisterClass *RC, Register VReg,
11891187
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const {
11901188
llvm_unreachable("Target didn't implement "
11911189
"TargetInstrInfo::loadRegFromStackSlot!");

‎llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -420,7 +420,7 @@ class StatepointState {
420420

421421
LLVM_DEBUG(dbgs() << "Insert spill before " << *InsertBefore);
422422
TII.storeRegToStackSlot(*MI.getParent(), InsertBefore, Reg, IsKill, FI,
423-
RC, &TRI, Register());
423+
RC, Register());
424424
}
425425
}
426426

@@ -429,15 +429,15 @@ class StatepointState {
429429
const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
430430
int FI = RegToSlotIdx[Reg];
431431
if (It != MBB->end()) {
432-
TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI, Register());
432+
TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, Register());
433433
return;
434434
}
435435

436436
// To insert reload at the end of MBB, insert it before last instruction
437437
// and then swap them.
438438
assert(!MBB->empty() && "Empty block");
439439
--It;
440-
TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI, Register());
440+
TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, Register());
441441
MachineInstr *Reload = It->getPrevNode();
442442
int Dummy = 0;
443443
(void)Dummy;

‎llvm/lib/CodeGen/InlineSpiller.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -473,7 +473,7 @@ bool InlineSpiller::hoistSpillInsideBB(LiveInterval &SpillLI,
473473
MachineInstrSpan MIS(MII, MBB);
474474
// Insert spill without kill flag immediately after def.
475475
TII.storeRegToStackSlot(*MBB, MII, SrcReg, false, StackSlot,
476-
MRI.getRegClass(SrcReg), &TRI, Register());
476+
MRI.getRegClass(SrcReg), Register());
477477
LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MII);
478478
for (const MachineInstr &MI : make_range(MIS.begin(), MII))
479479
getVDefInterval(MI, LIS);
@@ -1098,7 +1098,7 @@ void InlineSpiller::insertReload(Register NewVReg,
10981098

10991099
MachineInstrSpan MIS(MI, &MBB);
11001100
TII.loadRegFromStackSlot(MBB, MI, NewVReg, StackSlot,
1101-
MRI.getRegClass(NewVReg), &TRI, Register());
1101+
MRI.getRegClass(NewVReg), Register());
11021102

11031103
LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MI);
11041104

@@ -1134,7 +1134,7 @@ void InlineSpiller::insertSpill(Register NewVReg, bool isKill,
11341134

11351135
if (IsRealSpill)
11361136
TII.storeRegToStackSlot(MBB, SpillBefore, NewVReg, isKill, StackSlot,
1137-
MRI.getRegClass(NewVReg), &TRI, Register());
1137+
MRI.getRegClass(NewVReg), Register());
11381138
else
11391139
// Don't spill undef value.
11401140
// Anything works for undef, in particular keeping the memory
@@ -1708,7 +1708,7 @@ void HoistSpillHelper::hoistAllSpills() {
17081708
MachineBasicBlock::iterator MII = IPA.getLastInsertPointIter(OrigLI, *BB);
17091709
MachineInstrSpan MIS(MII, BB);
17101710
TII.storeRegToStackSlot(*BB, MII, LiveReg, false, Slot,
1711-
MRI.getRegClass(LiveReg), &TRI, Register());
1711+
MRI.getRegClass(LiveReg), Register());
17121712
LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MII);
17131713
for (const MachineInstr &MI : make_range(MIS.begin(), MII))
17141714
getVDefInterval(MI, LIS);

‎llvm/lib/CodeGen/RegAllocFast.cpp‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -594,8 +594,7 @@ void RegAllocFastImpl::spill(MachineBasicBlock::iterator Before,
594594
LLVM_DEBUG(dbgs() << " to stack slot #" << FI << '\n');
595595

596596
const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
597-
TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, TRI,
598-
VirtReg);
597+
TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, VirtReg);
599598
++NumStores;
600599

601600
MachineBasicBlock::iterator FirstTerm = MBB->getFirstTerminator();
@@ -652,7 +651,7 @@ void RegAllocFastImpl::reload(MachineBasicBlock::iterator Before,
652651
<< printReg(PhysReg, TRI) << '\n');
653652
int FI = getStackSpaceFor(VirtReg);
654653
const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
655-
TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, TRI, VirtReg);
654+
TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, VirtReg);
656655
++NumLoads;
657656
}
658657

@@ -1123,7 +1122,7 @@ bool RegAllocFastImpl::defineVirtReg(MachineInstr &MI, unsigned OpNum,
11231122
if (MO.isMBB()) {
11241123
MachineBasicBlock *Succ = MO.getMBB();
11251124
TII->storeRegToStackSlot(*Succ, Succ->begin(), PhysReg, Kill, FI,
1126-
&RC, TRI, VirtReg);
1125+
&RC, VirtReg);
11271126
++NumStores;
11281127
Succ->addLiveIn(PhysReg);
11291128
}

‎llvm/lib/CodeGen/RegisterScavenging.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -276,14 +276,14 @@ RegScavenger::spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
276276
": Cannot scavenge register without an emergency "
277277
"spill slot!");
278278
}
279-
TII->storeRegToStackSlot(*MBB, Before, Reg, true, FI, &RC, TRI, Register());
279+
TII->storeRegToStackSlot(*MBB, Before, Reg, true, FI, &RC, Register());
280280
MachineBasicBlock::iterator II = std::prev(Before);
281281

282282
unsigned FIOperandNum = getFrameIndexOperandNum(*II);
283283
TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
284284

285285
// Restore the scavenged register before its use (or first terminator).
286-
TII->loadRegFromStackSlot(*MBB, UseMI, Reg, FI, &RC, TRI, Register());
286+
TII->loadRegFromStackSlot(*MBB, UseMI, Reg, FI, &RC, Register());
287287
II = std::prev(UseMI);
288288

289289
FIOperandNum = getFrameIndexOperandNum(*II);

‎llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -198,7 +198,7 @@ void TargetFrameLowering::spillCalleeSavedRegister(
198198
} else {
199199
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
200200
TII->storeRegToStackSlot(SaveBlock, MI, Reg, true, CS.getFrameIdx(), RC,
201-
TRI, Register());
201+
Register());
202202
}
203203
}
204204

@@ -212,8 +212,7 @@ void TargetFrameLowering::restoreCalleeSavedRegister(
212212
.addReg(CS.getDstReg(), getKillRegState(true));
213213
} else {
214214
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
215-
TII->loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI,
216-
Register());
215+
TII->loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, Register());
217216
assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!");
218217
}
219218
}

‎llvm/lib/CodeGen/TargetInstrInfo.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -792,11 +792,11 @@ MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
792792
// code.
793793
BuildMI(*MBB, Pos, MI.getDebugLoc(), get(TargetOpcode::KILL)).add(MO);
794794
} else {
795-
storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, &TRI,
795+
storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC,
796796
Register());
797797
}
798798
} else
799-
loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, &TRI, Register());
799+
loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, Register());
800800

801801
return &*--Pos;
802802
}

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3732,7 +3732,7 @@ struct ScopedScavengeOrSpill {
37323732
}
37333733
FreeReg = SpillCandidate;
37343734
SpillFI = MaybeSpillFI->value();
3735-
TII.storeRegToStackSlot(MBB, MBBI, FreeReg, false, *SpillFI, &RC, &TRI,
3735+
TII.storeRegToStackSlot(MBB, MBBI, FreeReg, false, *SpillFI, &RC,
37363736
Register());
37373737
}
37383738

@@ -3745,8 +3745,7 @@ struct ScopedScavengeOrSpill {
37453745

37463746
~ScopedScavengeOrSpill() {
37473747
if (hasSpilled())
3748-
TII.loadRegFromStackSlot(MBB, MBBI, FreeReg, *SpillFI, &RC, &TRI,
3749-
Register());
3748+
TII.loadRegFromStackSlot(MBB, MBBI, FreeReg, *SpillFI, &RC, Register());
37503749
}
37513750

37523751
private:

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -5565,7 +5565,6 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
55655565
MachineBasicBlock::iterator MBBI,
55665566
Register SrcReg, bool isKill, int FI,
55675567
const TargetRegisterClass *RC,
5568-
const TargetRegisterInfo *TRI,
55695568
Register VReg,
55705569
MachineInstr::MIFlag Flags) const {
55715570
MachineFunction &MF = *MBB.getParent();
@@ -5579,7 +5578,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
55795578
bool Offset = true;
55805579
MCRegister PNRReg = MCRegister::NoRegister;
55815580
unsigned StackID = TargetStackID::Default;
5582-
switch (TRI->getSpillSize(*RC)) {
5581+
switch (RI.getSpillSize(*RC)) {
55835582
case 1:
55845583
if (AArch64::FPR8RegClass.hasSubClassEq(RC))
55855584
Opc = AArch64::STRBui;
@@ -5747,10 +5746,12 @@ static void loadRegPairFromStackSlot(const TargetRegisterInfo &TRI,
57475746
.addMemOperand(MMO);
57485747
}
57495748

5750-
void AArch64InstrInfo::loadRegFromStackSlot(
5751-
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg,
5752-
int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
5753-
Register VReg, MachineInstr::MIFlag Flags) const {
5749+
void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
5750+
MachineBasicBlock::iterator MBBI,
5751+
Register DestReg, int FI,
5752+
const TargetRegisterClass *RC,
5753+
Register VReg,
5754+
MachineInstr::MIFlag Flags) const {
57545755
MachineFunction &MF = *MBB.getParent();
57555756
MachineFrameInfo &MFI = MF.getFrameInfo();
57565757
MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
@@ -5762,7 +5763,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
57625763
bool Offset = true;
57635764
unsigned StackID = TargetStackID::Default;
57645765
Register PNRReg = MCRegister::NoRegister;
5765-
switch (TRI->getSpillSize(*RC)) {
5766+
switch (TRI.getSpillSize(*RC)) {
57665767
case 1:
57675768
if (AArch64::FPR8RegClass.hasSubClassEq(RC))
57685769
Opc = AArch64::LDRBui;
@@ -6394,10 +6395,10 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
63946395
"Mismatched register size in non subreg COPY");
63956396
if (IsSpill)
63966397
storeRegToStackSlot(MBB, InsertPt, SrcReg, SrcMO.isKill(), FrameIndex,
6397-
getRegClass(SrcReg), &TRI, Register());
6398+
getRegClass(SrcReg), Register());
63986399
else
63996400
loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex,
6400-
getRegClass(DstReg), &TRI, Register());
6401+
getRegClass(DstReg), Register());
64016402
return &*--InsertPt;
64026403
}
64036404

@@ -6415,8 +6416,7 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
64156416
assert(SrcMO.getSubReg() == 0 &&
64166417
"Unexpected subreg on physical register");
64176418
storeRegToStackSlot(MBB, InsertPt, AArch64::XZR, SrcMO.isKill(),
6418-
FrameIndex, &AArch64::GPR64RegClass, &TRI,
6419-
Register());
6419+
FrameIndex, &AArch64::GPR64RegClass, Register());
64206420
return &*--InsertPt;
64216421
}
64226422

@@ -6450,7 +6450,7 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
64506450
assert(TRI.getRegSizeInBits(*getRegClass(SrcReg)) ==
64516451
TRI.getRegSizeInBits(*FillRC) &&
64526452
"Mismatched regclass size on folded subreg COPY");
6453-
loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex, FillRC, &TRI,
6453+
loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex, FillRC,
64546454
Register());
64556455
MachineInstr &LoadMI = *--InsertPt;
64566456
MachineOperand &LoadDst = LoadMI.getOperand(0);

‎llvm/lib/Target/AArch64/AArch64InstrInfo.h‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -353,14 +353,13 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
353353

354354
void storeRegToStackSlot(
355355
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
356-
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
357-
const TargetRegisterInfo *TRI, Register VReg,
356+
bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
358357
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
359358

360359
void loadRegFromStackSlot(
361360
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
362361
Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
363-
const TargetRegisterInfo *TRI, Register VReg,
362+
Register VReg,
364363
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
365364

366365
// This tells target independent code that it is okay to pass instructions

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