Skip to content

Commit fd725db

Browse files
arsenmarsenm
committed
CodeGen: Remove TRI argument from reMaterialize
1 parent 532af14 commit fd725db

File tree

11 files changed

+17
-24
lines changed

11 files changed

+17
-24
lines changed

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -431,8 +431,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
431431
/// SubIdx.
432432
virtual void reMaterialize(MachineBasicBlock &MBB,
433433
MachineBasicBlock::iterator MI, Register DestReg,
434-
unsigned SubIdx, const MachineInstr &Orig,
435-
const TargetRegisterInfo &TRI) const;
434+
unsigned SubIdx, const MachineInstr &Orig) const;
436435

437436
/// Clones instruction or the whole instruction bundle \p Orig and
438437
/// insert into \p MBB before \p InsertBefore. The target may update operands

‎llvm/lib/CodeGen/LiveRangeEdit.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -182,7 +182,7 @@ SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
182182
bool Late, unsigned SubIdx,
183183
MachineInstr *ReplaceIndexMI) {
184184
assert(RM.OrigMI && "Invalid remat");
185-
TII.reMaterialize(MBB, MI, DestReg, SubIdx, *RM.OrigMI, tri);
185+
TII.reMaterialize(MBB, MI, DestReg, SubIdx, *RM.OrigMI);
186186
// DestReg of the cloned instruction cannot be Dead. Set isDead of DestReg
187187
// to false anyway in case the isDead flag of RM.OrigMI's dest register
188188
// is true.

‎llvm/lib/CodeGen/MachineSink.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -569,7 +569,7 @@ bool MachineSinking::PerformSinkAndFold(MachineInstr &MI,
569569
// Sink a copy of the instruction, replacing a COPY instruction.
570570
MachineBasicBlock::iterator InsertPt = SinkDst->getIterator();
571571
Register DstReg = SinkDst->getOperand(0).getReg();
572-
TII->reMaterialize(*SinkDst->getParent(), InsertPt, DstReg, 0, MI, *TRI);
572+
TII->reMaterialize(*SinkDst->getParent(), InsertPt, DstReg, 0, MI);
573573
New = &*std::prev(InsertPt);
574574
if (!New->getDebugLoc())
575575
New->setDebugLoc(SinkDst->getDebugLoc());

‎llvm/lib/CodeGen/TargetInstrInfo.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -445,10 +445,10 @@ bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
445445
return true;
446446
}
447447

448-
void TargetInstrInfo::reMaterialize(
449-
MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg,
450-
unsigned SubIdx, const MachineInstr &Orig,
451-
const TargetRegisterInfo & /*Remove me*/) const {
448+
void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
449+
MachineBasicBlock::iterator I,
450+
Register DestReg, unsigned SubIdx,
451+
const MachineInstr &Orig) const {
452452
MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
453453
MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
454454
MBB.insert(I, MI);

‎llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1891,7 +1891,7 @@ void PreRARematStage::rematerialize() {
18911891

18921892
// Rematerialize DefMI to its use block.
18931893
TII->reMaterialize(*InsertPos->getParent(), InsertPos, Reg,
1894-
AMDGPU::NoSubRegister, *DefMI, *DAG.TRI);
1894+
AMDGPU::NoSubRegister, *DefMI);
18951895
Remat.RematMI = &*std::prev(InsertPos);
18961896
DAG.LIS->InsertMachineInstrInMaps(*Remat.RematMI);
18971897

@@ -2043,8 +2043,7 @@ void PreRARematStage::finalizeGCNSchedStage() {
20432043
// Re-rematerialize MI at the end of its original region. Note that it may
20442044
// not be rematerialized exactly in the same position as originally within
20452045
// the region, but it should not matter much.
2046-
TII->reMaterialize(*MBB, InsertPos, Reg, AMDGPU::NoSubRegister, RematMI,
2047-
*DAG.TRI);
2046+
TII->reMaterialize(*MBB, InsertPos, Reg, AMDGPU::NoSubRegister, RematMI);
20482047
MachineInstr *NewMI = &*std::prev(InsertPos);
20492048
DAG.LIS->InsertMachineInstrInMaps(*NewMI);
20502049

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2548,8 +2548,8 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
25482548

25492549
void SIInstrInfo::reMaterialize(MachineBasicBlock &MBB,
25502550
MachineBasicBlock::iterator I, Register DestReg,
2551-
unsigned SubIdx, const MachineInstr &Orig,
2552-
const TargetRegisterInfo &RI) const {
2551+
unsigned SubIdx,
2552+
const MachineInstr &Orig) const {
25532553

25542554
// Try shrinking the instruction to remat only the part needed for current
25552555
// context.
@@ -2629,7 +2629,7 @@ void SIInstrInfo::reMaterialize(MachineBasicBlock &MBB,
26292629
break;
26302630
}
26312631

2632-
TargetInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig, RI);
2632+
TargetInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig);
26332633
}
26342634

26352635
std::pair<MachineInstr*, MachineInstr*>

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -316,8 +316,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
316316

317317
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
318318
Register DestReg, unsigned SubIdx,
319-
const MachineInstr &Orig,
320-
const TargetRegisterInfo &TRI) const override;
319+
const MachineInstr &Orig) const override;
321320

322321
// Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
323322
// instructions. Returns a pair of generated instructions.

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1653,8 +1653,7 @@ static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
16531653
void ARMBaseInstrInfo::reMaterialize(MachineBasicBlock &MBB,
16541654
MachineBasicBlock::iterator I,
16551655
Register DestReg, unsigned SubIdx,
1656-
const MachineInstr &Orig,
1657-
const TargetRegisterInfo &TRI) const {
1656+
const MachineInstr &Orig) const {
16581657
unsigned Opcode = Orig.getOpcode();
16591658
switch (Opcode) {
16601659
default: {

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.h‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -232,8 +232,7 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
232232

233233
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
234234
Register DestReg, unsigned SubIdx,
235-
const MachineInstr &Orig,
236-
const TargetRegisterInfo &TRI) const override;
235+
const MachineInstr &Orig) const override;
237236

238237
MachineInstr &
239238
duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,

‎llvm/lib/Target/X86/X86InstrInfo.cpp‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -957,8 +957,7 @@ bool X86InstrInfo::isReallyTriviallyReMaterializable(
957957
void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
958958
MachineBasicBlock::iterator I,
959959
Register DestReg, unsigned SubIdx,
960-
const MachineInstr &Orig,
961-
const TargetRegisterInfo &TRI) const {
960+
const MachineInstr &Orig) const {
962961
bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
963962
if (ClobbersEFLAGS && MBB.computeRegisterLiveness(&TRI, X86::EFLAGS, I) !=
964963
MachineBasicBlock::LQR_Dead) {

0 commit comments

Comments
 (0)