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kmpengkmpeng
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add tests for templated loads/stores
1 parent 8167a5b commit 0a747f5

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4 files changed

+373
-57
lines changed

4 files changed

+373
-57
lines changed

‎lib/API/DX/Device.cpp‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -78,10 +78,18 @@ static DXGI_FORMAT getRawDXFormat(const Resource &R) {
7878
return DXGI_FORMAT_UNKNOWN;
7979

8080
switch (R.BufferPtr->Format) {
81+
case DataFormat::Hex16:
82+
case DataFormat::UInt16:
83+
case DataFormat::Int16:
84+
case DataFormat::Float16:
8185
case DataFormat::Hex32:
8286
case DataFormat::UInt32:
8387
case DataFormat::Int32:
8488
case DataFormat::Float32:
89+
case DataFormat::Hex64:
90+
case DataFormat::UInt64:
91+
case DataFormat::Int64:
92+
case DataFormat::Float64:
8593
return DXGI_FORMAT_R32_TYPELESS;
8694
default:
8795
llvm_unreachable("Unsupported Resource format specified");
@@ -161,7 +169,7 @@ static D3D12_RESOURCE_DESC getResourceDescription(const Resource &R) {
161169
}
162170

163171
static D3D12_SHADER_RESOURCE_VIEW_DESC getSRVDescription(const Resource &R) {
164-
const uint32_t EltSize = R.getElementSize();
172+
const uint32_t EltSize = R.isByteAddressBuffer() ? 4 : R.getElementSize();
165173
const uint32_t NumElts = R.size() / EltSize;
166174

167175
llvm::outs() << " EltSize = " << EltSize << " NumElts = " << NumElts
@@ -197,7 +205,7 @@ static D3D12_SHADER_RESOURCE_VIEW_DESC getSRVDescription(const Resource &R) {
197205
}
198206

199207
static D3D12_UNORDERED_ACCESS_VIEW_DESC getUAVDescription(const Resource &R) {
200-
const uint32_t EltSize = R.getElementSize();
208+
const uint32_t EltSize = R.isByteAddressBuffer() ? 4 : R.getElementSize();
201209
const uint32_t NumElts = R.size() / EltSize;
202210
const uint32_t CounterOffset = getUAVBufferCounterOffset(R);
203211

‎test/Feature/ByteAddressBuffer/ByteAddressBuffers-16bit.test‎

Lines changed: 118 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,118 @@
1+
#--- source.hlsl
2+
3+
// This test checks that we will get the expected values from invoking
4+
// various `Load` and `Store` methods on `[RW]ByteAddressBuffer`.
5+
6+
// The expected behaviour is to load the values in `In0` and `In1` at the given
7+
// byte-offset, add them, and store the result at the respective offset in
8+
// `Out`. We expect each load and store to only access mapped resource data, so
9+
// `CheckAccessFullyMapped` should always return `true = 1`.
10+
11+
ByteAddressBuffer In0 : register(t0);
12+
ByteAddressBuffer In1 : register(t1);
13+
RWByteAddressBuffer Out : register(u0);
14+
RWBuffer<uint> Mapped : register(u0, space1);
15+
16+
[numthreads(4,1,1)]
17+
void main() {
18+
uint status;
19+
20+
int16_t U0 = In0.Load<int16_t>(0, status);
21+
Mapped[0] = CheckAccessFullyMapped(status);
22+
int16_t V0 = In1.Load<int16_t>(0);
23+
Out.Store<int16_t>(0, U0 + V0);
24+
25+
int16_t2 U1 = In0.Load<int16_t2>(8, status);
26+
Mapped[1] = CheckAccessFullyMapped(status);
27+
int16_t2 V1 = In1.Load<int16_t2>(8);
28+
Out.Store<int16_t2>(8, U1 + V1);
29+
30+
int16_t3 U2 = In0.Load<int16_t3>(16, status);
31+
Mapped[2] = CheckAccessFullyMapped(status);
32+
int16_t3 V2 = In1.Load<int16_t3>(16);
33+
Out.Store<int16_t3>(16, U2 + V2);
34+
35+
int16_t4 U3 = In0.Load<int16_t4>(24, status);
36+
Mapped[3] = CheckAccessFullyMapped(status);
37+
int16_t4 V3 = In1.Load<int16_t4>(24);
38+
Out.Store<int16_t4>(24, U3 + V3);
39+
}
40+
41+
//--- pipeline.yaml
42+
43+
---
44+
Shaders:
45+
- Stage: Compute
46+
Entry: main
47+
DispatchSize: [4, 1, 1]
48+
Buffers:
49+
- Name: In0
50+
Format: Int16
51+
Stride: 2
52+
Data: [ 1, 2, 3, 4, 5, 6, 7, 8,
53+
9, 10, 11, 12, 13, 14, 15, 16 ]
54+
- Name: In1
55+
Format: Hex16
56+
Stride: 2
57+
Data: [ 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700, 0x800,
58+
0x900, 0xA00, 0xB00, 0xC00, 0xD00, 0xE00, 0xF00, 0x1000 ]
59+
- Name: Out
60+
Format: Hex16
61+
Stride: 2
62+
FillSize: 32
63+
- Name: ExpectedOut
64+
Format: Hex16
65+
Stride: 2
66+
Data: [ 0x101, 0x000, 0x000, 0x000, 0x505, 0x606, 0x000, 0x000,
67+
0x909, 0xA0A, 0xB0B, 0x000, 0xD0D, 0xE0E, 0xF0F, 0x1010 ]
68+
- Name: Mapped
69+
Format: Int32
70+
Stride: 4
71+
FillSize: 16
72+
- Name: ExpectedMapped
73+
Format: Int32
74+
Stride: 4
75+
Data: [ 1, 1, 1, 1 ]
76+
Results:
77+
- Result: Test0
78+
Rule: BufferExact
79+
Actual: Out
80+
Expected: ExpectedOut
81+
- Result: Test1
82+
Rule: BufferExact
83+
Actual: Mapped
84+
Expected: ExpectedMapped
85+
DescriptorSets:
86+
- Resources:
87+
- Name: In0
88+
Kind: ByteAddressBuffer
89+
DirectXBinding:
90+
Register: 0
91+
Space: 0
92+
- Name: In1
93+
Kind: ByteAddressBuffer
94+
DirectXBinding:
95+
Register: 1
96+
Space: 0
97+
- Name: Out
98+
Kind: RWByteAddressBuffer
99+
DirectXBinding:
100+
Register: 0
101+
Space: 0
102+
- Name: Mapped
103+
Kind: RWBuffer
104+
DirectXBinding:
105+
Register: 0
106+
Space: 1
107+
...
108+
#--- end
109+
110+
# UNSUPPORTED: Vulkan, Metal
111+
112+
# Unimplemented https://github.com/llvm/llvm-project/issues/108058
113+
# XFAIL: Clang
114+
115+
# REQUIRES: Int16
116+
# RUN: split-file %s %t
117+
# RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl
118+
# RUN: %offloader %t/pipeline.yaml %t.o

‎test/Feature/ByteAddressBuffer/ByteAddressBuffers-64bit.test‎

Lines changed: 118 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,118 @@
1+
#--- source.hlsl
2+
3+
// This test checks that we will get the expected values from invoking
4+
// various `Load` and `Store` methods on `[RW]ByteAddressBuffer`.
5+
6+
// The expected behaviour is to load the values in `In0` and `In1` at the given
7+
// byte-offset, add them, and store the result at the respective offset in
8+
// `Out`. We expect each load and store to only access mapped resource data, so
9+
// `CheckAccessFullyMapped` should always return `true = 1`.
10+
11+
ByteAddressBuffer In0 : register(t0);
12+
ByteAddressBuffer In1 : register(t1);
13+
RWByteAddressBuffer Out : register(u0);
14+
RWBuffer<uint> Mapped : register(u0, space1);
15+
16+
[numthreads(4,1,1)]
17+
void main() {
18+
uint status;
19+
20+
int64_t U0 = In0.Load<int64_t>(0, status);
21+
Mapped[0] = CheckAccessFullyMapped(status);
22+
int64_t V0 = In1.Load<int64_t>(0);
23+
Out.Store<int64_t>(0, U0 + V0);
24+
25+
int64_t2 U1 = In0.Load<int64_t2>(32, status);
26+
Mapped[1] = CheckAccessFullyMapped(status);
27+
int64_t2 V1 = In1.Load<int64_t2>(32);
28+
Out.Store<int64_t2>(32, U1 + V1);
29+
30+
int64_t3 U2 = In0.Load<int64_t3>(64, status);
31+
Mapped[2] = CheckAccessFullyMapped(status);
32+
int64_t3 V2 = In1.Load<int64_t3>(64);
33+
Out.Store<int64_t3>(64, U2 + V2);
34+
35+
int64_t4 U3 = In0.Load<int64_t4>(96, status);
36+
Mapped[3] = CheckAccessFullyMapped(status);
37+
int64_t4 V3 = In1.Load<int64_t4>(96);
38+
Out.Store<int64_t4>(96, U3 + V3);
39+
}
40+
41+
//--- pipeline.yaml
42+
43+
---
44+
Shaders:
45+
- Stage: Compute
46+
Entry: main
47+
DispatchSize: [4, 1, 1]
48+
Buffers:
49+
- Name: In0
50+
Format: Int64
51+
Stride: 8
52+
Data: [ 1, 2, 3, 4, 5, 6, 7, 8,
53+
9, 10, 11, 12, 13, 14, 15, 16 ]
54+
- Name: In1
55+
Format: Hex64
56+
Stride: 8
57+
Data: [ 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700, 0x800,
58+
0x900, 0xA00, 0xB00, 0xC00, 0xD00, 0xE00, 0xF00, 0x1000 ]
59+
- Name: Out
60+
Format: Hex64
61+
Stride: 8
62+
FillSize: 128
63+
- Name: ExpectedOut
64+
Format: Hex64
65+
Stride: 8
66+
Data: [ 0x101, 0x000, 0x000, 0x000, 0x505, 0x606, 0x000, 0x000,
67+
0x909, 0xA0A, 0xB0B, 0x000, 0xD0D, 0xE0E, 0xF0F, 0x1010 ]
68+
- Name: Mapped
69+
Format: Int32
70+
Stride: 4
71+
FillSize: 16
72+
- Name: ExpectedMapped
73+
Format: Int32
74+
Stride: 4
75+
Data: [ 1, 1, 1, 1 ]
76+
Results:
77+
- Result: Test0
78+
Rule: BufferExact
79+
Actual: Out
80+
Expected: ExpectedOut
81+
- Result: Test1
82+
Rule: BufferExact
83+
Actual: Mapped
84+
Expected: ExpectedMapped
85+
DescriptorSets:
86+
- Resources:
87+
- Name: In0
88+
Kind: ByteAddressBuffer
89+
DirectXBinding:
90+
Register: 0
91+
Space: 0
92+
- Name: In1
93+
Kind: ByteAddressBuffer
94+
DirectXBinding:
95+
Register: 1
96+
Space: 0
97+
- Name: Out
98+
Kind: RWByteAddressBuffer
99+
DirectXBinding:
100+
Register: 0
101+
Space: 0
102+
- Name: Mapped
103+
Kind: RWBuffer
104+
DirectXBinding:
105+
Register: 0
106+
Space: 1
107+
...
108+
#--- end
109+
110+
# UNSUPPORTED: Vulkan, Metal
111+
112+
# Unimplemented https://github.com/llvm/llvm-project/issues/108058
113+
# XFAIL: Clang
114+
115+
# REQUIRES: Int64
116+
# RUN: split-file %s %t
117+
# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
118+
# RUN: %offloader %t/pipeline.yaml %t.o

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