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Pull request #90: Develop
Merge in MCU16CE/dspic33-dsc-bootloader-code-examples from develop to master Squashed commit of the following: commit af1e608 Merge: 9a0c379 af68f8c Author: Anastasia Wyatt <Tess.Wyatt@microchip.com> Date: Wed Jun 11 11:14:37 2025 -0600 Pull request #88: Update version and changelog, MCU16GITHUB-1586 - remove leading space Merge in MCU16CE/dspic33-dsc-bootloader-code-examples from ~C74569/dspic33-dsc-bootloader-code-examples:bugfix/CC16BOOT-8484-update-changelog-and-versions-in-dspic33a_bootloader_and_firmware_upgrade_demo_ to develop * commit 'af68f8ceb24e43f6a95498c596c0252c4bb14666': Ensure inner project versions match outer version Remove leading space from secure boot main.json and update changelog Update changelog Remove leading space Update version and changelog commit af68f8c Author: Anastasia Wyatt <Tess.Wyatt@microchip.com> Date: Wed Jun 11 09:46:05 2025 -0700 Ensure inner project versions match outer version commit 124e97a Author: Anastasia Wyatt <Tess.Wyatt@microchip.com> Date: Tue Jun 10 14:40:36 2025 -0700 Remove leading space from secure boot main.json and update changelog commit 1c60971 Author: Anastasia Wyatt <Tess.Wyatt@microchip.com> Date: Tue Jun 10 14:33:37 2025 -0700 Update changelog commit b899a6a Author: Anastasia Wyatt <Tess.Wyatt@microchip.com> Date: Tue Jun 10 14:29:42 2025 -0700 Remove leading space commit a58798e Author: Anastasia Wyatt <Tess.Wyatt@microchip.com> Date: Tue Jun 10 14:20:21 2025 -0700 Update version and changelog commit 9a0c379 Merge: a7974f0 ad7cf89 Author: Anastasia Wyatt <Tess.Wyatt@microchip.com> Date: Tue Jun 10 13:00:15 2025 -0600 Pull request #87: Bugfix/CC16BOOT-8480 update dspic33a bootloader and firmware upgrade demo Merge in MCU16CE/dspic33-dsc-bootloader-code-examples from ~C74569/dspic33-dsc-bootloader-code-examples:bugfix/CC16BOOT-8480-update-dspic33a_bootloader_and_firmware_upgrade_demo to develop * commit 'ad7cf89d9e4f229d1bd1b5df9b26ca5db7a4da4e': Update flash protection project Update app project Update boot project commit ad7cf89 Author: Anastasia Wyatt <Tess.Wyatt@microchip.com> Date: Tue Jun 10 11:33:44 2025 -0700 Update flash protection project commit ca15177 Author: Anastasia Wyatt <Tess.Wyatt@microchip.com> Date: Tue Jun 10 11:29:51 2025 -0700 Update app project commit 72afbe7 Author: Anastasia Wyatt <Tess.Wyatt@microchip.com> Date: Tue Jun 10 11:28:49 2025 -0700 Update boot project
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‎.main-meta/main.json‎

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"content": {
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"metaDataVersion": "1.3.0",
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"name": "com.microchip.mplabx.project.dspic33-dsc-bootloader-code-examples",
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"version": "1.2.1",
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"version": "1.2.2",
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"displayName": "dsPIC33 DSC Bootloader Code Examples",
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"projectName": "dspic33-dsc-bootloader-code-examples",
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"shortDescription": "dsPIC33 DSC Bootloader Code Examples",

‎changelog.md‎

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# dsPIC33 DSC Bootloader Code Examples v1.2.2
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### Release Highlights
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* Updated Clock PLIB version from v1.1.0 to v1.1.2 in "dspic33a_bootloader_and_firmware_upgrade_demo".
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* Removed invalid space from the device name in the "dspic33a_bootloader_and_firmware_upgrade_demo" and "dspic33a_secure_boot" main.json files.
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### Features Added\Updated
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* Updated Clock PLIB version from v1.1.0 to v1.1.2 in "dspic33a_bootloader_and_firmware_upgrade_demo".
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* Removed invalid space from the device name in the "dspic33a_bootloader_and_firmware_upgrade_demo" and "dspic33a_secure_boot" main.json files.
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# dsPIC33 DSC Bootloader Code Examples v1.2.1
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### Release Highlights
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* Corrected version number of "dspic33a Secure Boot and Secure Firmware Upgrade Demo".

‎dspic33a_bootloader_and_firmware_upgrade_demo/.main-meta/main.json‎

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"content": {
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"metaDataVersion": "1.3.0",
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"name": "com.microchip.mplabx.project.dspic33a-bootloader-and-firmware-upgrade-demo",
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"version": "1.1.0",
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"version": "1.2.2",
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"displayName": "dsPIC33a Bootloader and Firmware Upgrade Demo",
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"projectName": "dspic33a-bootloader-and-firmware-upgrade-demo",
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"shortDescription": "This MPLAB® X IDE example demonstrates how to perform secure boot authentication and firmware upgrade via UART with Microchip Device Firmware Update Protocol (M-DFU) and CRC32 verification within MCC Melody.",
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"content": {
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"metaDataVersion": "1.0.0",
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"category": "com.microchip.device",
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"name": " dsPIC33AK128MC106",
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"name": "dsPIC33AK128MC106",
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"versionRange": "*"
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}
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},

‎dspic33a_bootloader_and_firmware_upgrade_demo/app.X/app.mc3‎

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‎dspic33a_bootloader_and_firmware_upgrade_demo/app.X/mcc_generated_files/system/clock.h‎

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*
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* @brief Clock configurator driver for System and Peripheral Clock using dsPIC MCUs.
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*
10-
* @version PLIB Version 1.1.0
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* @skipline @version PLIB Version 1.1.2
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*
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* @skipline Device : dsPIC33AK128MC106
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*/

‎dspic33a_bootloader_and_firmware_upgrade_demo/app.X/mcc_generated_files/system/clock_types.h‎

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*
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* @brief This is the generated driver types header file for the CLOCK driver
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*
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* @version PLIB Version 1.1.0
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* @skipline @version PLIB Version 1.1.2
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*
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* @skipline Device : dsPIC33AK128MC106
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*/
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*/
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enum CLOCK_GENERATOR
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{
46-
CLOCK_GENERATOR_1, /**< Clock Generator 1 */
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CLOCK_GENERATOR_2, /**< Clock Generator 2 */
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CLOCK_GENERATOR_3, /**< Clock Generator 3 */
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CLOCK_GENERATOR_1 = 1, /**< Clock Generator 1 */
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CLOCK_GENERATOR_2 = 2, /**< Clock Generator 2 */
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CLOCK_GENERATOR_3 = 3, /**< Clock Generator 3 */
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CLOCK_SYSTEM = 1, /**< Clock for System */
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CLOCK_FRC = 2, /**< Clock for FRC */

‎dspic33a_bootloader_and_firmware_upgrade_demo/app.X/mcc_generated_files/system/src/clock.c‎

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*
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* @brief This is the generated source file for CLOCK driver
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*
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* @version PLIB Version 1.1.0
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* @version PLIB Version 1.1.2
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*
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* @skipline Device : dsPIC33AK128MC106
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*/
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#include "../clock.h"
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#include "../clock_types.h"
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45+
#define PLL1FOUT_SOURCE 0x5U
46+
#define PLL2VCODIV_SOURCE 0x8U
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// Section: Static Variables
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4751
void CLOCK_Initialize(void)
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{
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/*
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PLL 1 VCO Out frequency : 200 MHz
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*/
60-
61-
/* Always switch to FRC before making clock changes. */
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CLK1CONbits.NOSC = 1; // FRC_CLK
63-
CLK1CONbits.OSWEN = 1;
64-
while(CLK1CONbits.OSWEN){}
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65+
66+
//If CLK GEN 1 (system clock) is using a PLL, switch to FRC to avoid risk of over-clocking the CPU while changing PLL settings
67+
if((CLK1CONbits.COSC >= PLL1FOUT_SOURCE) && (CLK1CONbits.COSC <= PLL2VCODIV_SOURCE))
68+
{
69+
CLK1CONbits.NOSC = 1U; //FRC as source
70+
CLK1CONbits.OSWEN = 1U;
71+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
72+
while(CLK1CONbits.OSWEN == 1U){};
73+
#endif
74+
}
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6676
// NOSC FRC Oscillator; OE enabled; SIDL disabled; ON enabled; BOSC Serial Test Mode clock (PGC); FSCMEN disabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL disabled; EXTCFEN disabled; FOUTSWEN disabled; RIS disabled; PLLSWEN disabled;
67-
PLL1CON = 0x000129100UL;
77+
PLL1CON = 0x9100UL;
6878
// POSTDIV2 2x divide; POSTDIV1 4x divide; PLLFBDIV 200; PLLPRE 1;
6979
PLL1DIV = 0x100C822UL;
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//Enable PLL Input and Feedback Divider update
7181
PLL1CONbits.PLLSWEN = 1U;
82+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
7283
while (PLL1CONbits.PLLSWEN == 1){};
84+
#endif
7385
PLL1CONbits.FOUTSWEN = 1U;
86+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
7487
while (PLL1CONbits.FOUTSWEN == 1U){};
75-
88+
#endif
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//enable clock switching
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PLL1CONbits.OSWEN = 1U;
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#ifndef __MPLAB_DEBUGGER_SIMULATOR
7892
//wait for switching
7993
while(PLL1CONbits.OSWEN == 1U){};
8094
//wait for clock to be ready
8195
while(OSCCTRLbits.PLL1RDY == 0U){};
96+
#endif
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8398
//Configure VCO Divider
8499
// INTDIV 4;
85100
VCO1DIV = 0x40000UL;
86101
//enable PLL VCO divider
87-
PLL1CONbits.DIVSWEN = 1U;
102+
PLL1CONbits.DIVSWEN = 1U;
103+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
88104
//wait for setup complete
89105
while(PLL1CONbits.DIVSWEN == 1U){};
106+
#endif
107+
//Clearing ON shuts down oscillator when no downstream clkgen or peripheral is requesting the clock
108+
PLL1CONbits.ON = 0U;
90109

91-
// NOSC FRC Oscillator; OE enabled; SIDL disabled; ON enabled; BOSC FRC Oscillator; FSCMEN disabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL External clock fail detection module #1; EXTCFEN disabled; RIS disabled;
92-
CLK1CON = 0x000129500UL;
110+
// NOSC PLL1 Out output; OE enabled; SIDL disabled; ON enabled; BOSC Backup FRC Oscillator; FSCMEN enabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL External clock fail detection module #1; EXTCFEN disabled; RIS disabled;
111+
CLK1CON = 0x129500UL;
93112
// FRACDIV 0; INTDIV 0;
94113
CLK1DIV = 0x0UL;
95114
//enable clock switching
96-
CLK1CONbits.OSWEN = 1U;
115+
CLK1CONbits.OSWEN = 1U;
116+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
97117
//wait for clock switching complete
98118
while(CLK1CONbits.OSWEN == 1U){};
119+
#endif
99120

100-
// NOSC FRC Oscillator; OE enabled; SIDL disabled; ON enabled; BOSC Serial Test Mode clock (PGC); FSCMEN disabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL External clock fail detection module #1; EXTCFEN disabled; RIS disabled;
101-
CLK2CON = 0x000129101UL;
121+
// NOSC FRC Oscillator; OE enabled; SIDL disabled; ON enabled; BOSC Backup FRC Oscillator; FSCMEN disabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL External clock fail detection module #1; EXTCFEN disabled; RIS disabled;
122+
CLK2CON = 0x29101UL;
102123
//enable clock switching
103-
CLK2CONbits.OSWEN = 1U;
124+
CLK2CONbits.OSWEN = 1U;
125+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
104126
//wait for clock switching complete
105127
while(CLK2CONbits.OSWEN == 1U){};
128+
#endif
106129

107-
// NOSC Backup FRC Oscillator; OE enabled; SIDL disabled; ON enabled; BOSC Serial Test Mode clock (PGC); FSCMEN disabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL External clock fail detection module #1; EXTCFEN disabled; RIS disabled;
108-
CLK3CON = 0x000129202UL;
130+
// NOSC Backup FRC Oscillator; OE enabled; SIDL disabled; ON enabled; BOSC FRC Oscillator; FSCMEN disabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL External clock fail detection module #1; EXTCFEN disabled; RIS disabled;
131+
CLK3CON = 0x19202UL;
109132
//enable clock switching
110-
CLK3CONbits.OSWEN = 1U;
133+
CLK3CONbits.OSWEN = 1U;
134+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
111135
//wait for clock switching complete
112-
while(CLK3CONbits.OSWEN == 1U){};
136+
while(CLK3CONbits.OSWEN == 1U){};
137+
#endif
138+
139+
113140

114-
// Allow clocks to disable unless required by a peripheral
115-
CLK1CONbits.ON = 0;
116-
CLK2CONbits.ON = 0;
117-
CLK3CONbits.ON = 0;
118-
PLL1CONbits.ON = 0;
119141
}
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