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Add AArch64 instructions: FCVTZU, UCVTF, SQXTN, UQXTN.
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‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/asm/aarch64/AArch64ASIMDAssembler.java‎

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Original file line numberDiff line numberDiff line change
@@ -625,16 +625,20 @@ public enum ASIMDInstruction {
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CMLT_ZERO(0b01010 << 12),
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ABS(0b01011 << 12),
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XTN(0b10010 << 12),
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SQXTN(0b10100 << 12),
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UQXTN(UBit | 0b10100 << 12),
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/* size 0x */
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FCVTN(0b10110 << 12),
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FCVTL(0b10111 << 12),
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SCVTF(0b11101 << 12),
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UCVTF(UBit | 0b11101 << 12),
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/* size 1x */
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FCMGT_ZERO(0b01100 << 12),
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FCMEQ_ZERO(0b01101 << 12),
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FCMLT_ZERO(0b01110 << 12),
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FABS(0b01111 << 12),
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FCVTZS(0b11011 << 12),
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FCVTZU(UBit | 0b11011 << 12),
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/* UBit 1, size xx */
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REV32(UBit | 0b00000 << 12),
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CMGE_ZERO(UBit | 0b01000 << 12),
@@ -1979,6 +1983,25 @@ public void fcvtzsVV(ASIMDSize size, ElementSize eSize, Register dst, Register s
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twoRegMiscEncoding(ASIMDInstruction.FCVTZS, size, elemSize1X(eSize), dst, src);
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}
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/**
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* Floating-point convert to unsigned integer, rounding toward zero.<br>
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*
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* @param size register size.
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* @param eSize source element size. Must be ElementSize.Word or ElementSize.DoubleWord.
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* ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is
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* performed on more than one element).
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* @param dst SIMD register.
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* @param src SIMD register.
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*/
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public void fcvtzuVV(ASIMDSize size, ElementSize eSize, Register dst, Register src) {
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assert usesMultipleLanes(size, eSize) : "Must use multiple lanes " + size + " " + eSize;
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assert dst.getRegisterCategory().equals(SIMD) : dst;
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assert src.getRegisterCategory().equals(SIMD) : src;
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assert eSize == ElementSize.Word || eSize == ElementSize.DoubleWord : eSize;
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twoRegMiscEncoding(ASIMDInstruction.FCVTZU, size, elemSize1X(eSize), dst, src);
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}
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/**
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* C7.2.97 floating point divide vector.<br>
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*
@@ -2734,6 +2757,25 @@ public void scvtfVV(ASIMDSize size, ElementSize eSize, Register dst, Register sr
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twoRegMiscEncoding(ASIMDInstruction.SCVTF, size, elemSize0X(eSize), dst, src);
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}
27362759

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/**
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* Unsigned integer convert to floating-point.<br>
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*
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* @param size register size.
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* @param eSize source element size. Must be ElementSize.Word or ElementSize.DoubleWord.
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* ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is
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* performed on more than one element).
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* @param dst SIMD register.
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* @param src SIMD register.
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*/
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public void ucvtfVV(ASIMDSize size, ElementSize eSize, Register dst, Register src) {
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assert usesMultipleLanes(size, eSize) : "Must use multiple lanes " + size + " " + eSize;
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assert dst.getRegisterCategory().equals(SIMD) : dst;
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assert src.getRegisterCategory().equals(SIMD) : src;
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assert eSize == ElementSize.Word || eSize == ElementSize.DoubleWord : eSize;
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twoRegMiscEncoding(ASIMDInstruction.UCVTF, size, elemSize0X(eSize), dst, src);
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}
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/**
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* C7.2.239 SHA1 hash update.<br>
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*
@@ -4096,6 +4138,48 @@ public void xtn2VV(ElementSize dstESize, Register dst, Register src) {
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twoRegMiscEncoding(ASIMDInstruction.XTN, true, elemSizeXX(dstESize), dst, src);
40974139
}
40984140

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/**
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* Signed saturating extract Narrow.<br>
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* <p>
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* From the manual: "This instruction reads each vector element from the source SIMD register,
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* saturates each value to half the original width, places the result into a vector, and writes
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* the vector to the destination SIMD register. All the values in this instruction are signed
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* integer values."
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*
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* @param dstESize destination element size. Cannot be ElementSize.DoubleWord. The source
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* element size is twice this width.
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* @param dst SIMD register.
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* @param src SIMD register.
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*/
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public void sqxtnVV(ElementSize dstESize, Register dst, Register src) {
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assert dst.getRegisterCategory().equals(SIMD) : dst;
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assert src.getRegisterCategory().equals(SIMD) : src;
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assert dstESize != ElementSize.DoubleWord : dstESize;
4158+
4159+
twoRegMiscEncoding(ASIMDInstruction.SQXTN, false, elemSizeXX(dstESize), dst, src);
4160+
}
4161+
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/**
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* Unsigned saturating extract Narrow.<br>
4164+
* <p>
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* From the manual: "This instruction reads each vector element from the source SIMD register,
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* saturates each value to half the original width, places the result into a vector, and writes
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* the vector to the destination SIMD register. All the values in this instruction are unsigned
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* integer values."
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*
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* @param dstESize destination element size. Cannot be ElementSize.DoubleWord. The source
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* element size is twice this width.
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* @param dst SIMD register.
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* @param src SIMD register.
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*/
4175+
public void uqxtnVV(ElementSize dstESize, Register dst, Register src) {
4176+
assert dst.getRegisterCategory().equals(SIMD) : dst;
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assert src.getRegisterCategory().equals(SIMD) : src;
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assert dstESize != ElementSize.DoubleWord : dstESize;
4179+
4180+
twoRegMiscEncoding(ASIMDInstruction.UQXTN, false, elemSizeXX(dstESize), dst, src);
4181+
}
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40994183
/**
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* C7.2.403 Zip vectors (primary).
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* <p>

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/asm/aarch64/AArch64Assembler.java‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,7 @@
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import static jdk.graal.compiler.asm.aarch64.AArch64Assembler.Instruction.FCVTAS;
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import static jdk.graal.compiler.asm.aarch64.AArch64Assembler.Instruction.FCVTMS;
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import static jdk.graal.compiler.asm.aarch64.AArch64Assembler.Instruction.FCVTZS;
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import static jdk.graal.compiler.asm.aarch64.AArch64Assembler.Instruction.FCVTZU;
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import static jdk.graal.compiler.asm.aarch64.AArch64Assembler.Instruction.FDIV;
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import static jdk.graal.compiler.asm.aarch64.AArch64Assembler.Instruction.FMADD;
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import static jdk.graal.compiler.asm.aarch64.AArch64Assembler.Instruction.FMAX;
@@ -151,6 +152,7 @@
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import static jdk.graal.compiler.asm.aarch64.AArch64Assembler.Instruction.TBNZ;
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import static jdk.graal.compiler.asm.aarch64.AArch64Assembler.Instruction.TBZ;
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import static jdk.graal.compiler.asm.aarch64.AArch64Assembler.Instruction.UBFM;
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import static jdk.graal.compiler.asm.aarch64.AArch64Assembler.Instruction.UCVTF;
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import static jdk.graal.compiler.asm.aarch64.AArch64Assembler.Instruction.UDIV;
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import static jdk.graal.compiler.asm.aarch64.AArch64Assembler.InstructionType.FP32;
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import static jdk.graal.compiler.asm.aarch64.AArch64Assembler.InstructionType.FP64;
@@ -1013,7 +1015,9 @@ public enum Instruction {
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FCVTMS(0x00100000),
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FCVTZS(0x00180000),
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FCVTZU(0x00190000),
10161019
SCVTF(0x00020000),
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UCVTF(0x00030000),
10171021

10181022
FABS(0x00008000),
10191023
FSQRT(0x00018000),
@@ -3524,6 +3528,20 @@ public void fcvtzs(int dstSize, int srcSize, Register dst, Register src) {
35243528
fcvtCpuFpuInstruction(FCVTZS, dst, src, generalFromSize(dstSize), floatFromSize(srcSize));
35253529
}
35263530

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/**
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* Floating-point Convert to Unsigned integer, rounding toward Zero.
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*
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* @param dstSize size of integer register. 32 or 64.
3535+
* @param srcSize size of floating point register. 32 or 64.
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* @param dst general purpose register. May not be null, the zero-register or the stackpointer.
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* @param src floating point register. May not be null.
3538+
*/
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public void fcvtzu(int dstSize, int srcSize, Register dst, Register src) {
3540+
assert verifySizesAndRegistersRF(dstSize, srcSize, dst, src);
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3542+
fcvtCpuFpuInstruction(FCVTZU, dst, src, generalFromSize(dstSize), floatFromSize(srcSize));
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}
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35273545
/* Convert from Integer (5.7.4.2) */
35283546
/**
35293547
* C7.2.236 Signed integer Convert to Floating-point (scalar).
@@ -3539,6 +3557,20 @@ public void scvtf(int dstSize, int srcSize, Register dst, Register src) {
35393557
fcvtCpuFpuInstruction(SCVTF, dst, src, floatFromSize(dstSize), generalFromSize(srcSize));
35403558
}
35413559

3560+
/**
3561+
* Unsigned integer Convert to Floating-point (scalar).
3562+
*
3563+
* @param dstSize size of floating point register. 32 or 64.
3564+
* @param srcSize size of integer register. 32 or 64.
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* @param dst floating point register. May not be null.
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* @param src general purpose register. May not be null or the stackpointer.
3567+
*/
3568+
public void ucvtf(int dstSize, int srcSize, Register dst, Register src) {
3569+
assert verifySizesAndRegistersFZ(dstSize, srcSize, dst, src);
3570+
3571+
fcvtCpuFpuInstruction(UCVTF, dst, src, floatFromSize(dstSize), generalFromSize(srcSize));
3572+
}
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private void fcvtCpuFpuInstruction(Instruction instr, Register dst, Register src, InstructionType type1, InstructionType type2) {
35433575
emitInt(type1.encoding | type2.encoding | instr.encoding | FpConvertOp | rd(dst) | rs1(src));
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}

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