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NadeemYaseenNadeemYaseen
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Added SIM change files from 1.5.7
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3 files changed

+231
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‎blackbox_models/cell_sim_blackbox.v‎

Lines changed: 77 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,62 @@ module DLY_SEL_DCODER (
9494
input logic DLY_ADJ,
9595
input logic DLY_INCDEC,
9696
input logic [4:0] DLY_ADDR,
97-
output reg [2:0] DLY_CNTRL[31:0]
97+
output reg [2:0] DLY0_CNTRL,
98+
output reg [2:0] DLY1_CNTRL,
99+
output reg [2:0] DLY2_CNTRL,
100+
output reg [2:0] DLY3_CNTRL,
101+
output reg [2:0] DLY4_CNTRL,
102+
output reg [2:0] DLY5_CNTRL,
103+
output reg [2:0] DLY6_CNTRL,
104+
output reg [2:0] DLY7_CNTRL,
105+
output reg [2:0] DLY8_CNTRL,
106+
output reg [2:0] DLY9_CNTRL,
107+
output reg [2:0] DLY10_CNTRL,
108+
output reg [2:0] DLY11_CNTRL,
109+
output reg [2:0] DLY12_CNTRL,
110+
output reg [2:0] DLY13_CNTRL,
111+
output reg [2:0] DLY14_CNTRL,
112+
output reg [2:0] DLY15_CNTRL,
113+
output reg [2:0] DLY16_CNTRL,
114+
output reg [2:0] DLY17_CNTRL,
115+
output reg [2:0] DLY18_CNTRL,
116+
output reg [2:0] DLY19_CNTRL
117+
);
118+
endmodule
119+
`endcelldefine
120+
//
121+
// DLY_SEL_DECODER black box model
122+
// Address Decoder
123+
//
124+
// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
125+
//
126+
`celldefine
127+
(* blackbox *)
128+
module DLY_SEL_DECODER (
129+
input logic DLY_LOAD,
130+
input logic DLY_ADJ,
131+
input logic DLY_INCDEC,
132+
input logic [4:0] DLY_ADDR,
133+
output reg [2:0] DLY0_CNTRL,
134+
output reg [2:0] DLY1_CNTRL,
135+
output reg [2:0] DLY2_CNTRL,
136+
output reg [2:0] DLY3_CNTRL,
137+
output reg [2:0] DLY4_CNTRL,
138+
output reg [2:0] DLY5_CNTRL,
139+
output reg [2:0] DLY6_CNTRL,
140+
output reg [2:0] DLY7_CNTRL,
141+
output reg [2:0] DLY8_CNTRL,
142+
output reg [2:0] DLY9_CNTRL,
143+
output reg [2:0] DLY10_CNTRL,
144+
output reg [2:0] DLY11_CNTRL,
145+
output reg [2:0] DLY12_CNTRL,
146+
output reg [2:0] DLY13_CNTRL,
147+
output reg [2:0] DLY14_CNTRL,
148+
output reg [2:0] DLY15_CNTRL,
149+
output reg [2:0] DLY16_CNTRL,
150+
output reg [2:0] DLY17_CNTRL,
151+
output reg [2:0] DLY18_CNTRL,
152+
output reg [2:0] DLY19_CNTRL
98153
);
99154
endmodule
100155
`endcelldefine
@@ -107,9 +162,28 @@ endmodule
107162
`celldefine
108163
(* blackbox *)
109164
module DLY_VALUE_MUX (
110-
input logic [5:0] DLY_TAP_VAL_ARRAY[19:0],
165+
input logic [5:0] DLY_TAP0_VAL,
166+
input logic [5:0] DLY_TAP1_VAL,
167+
input logic [5:0] DLY_TAP2_VAL,
168+
input logic [5:0] DLY_TAP3_VAL,
169+
input logic [5:0] DLY_TAP4_VAL,
170+
input logic [5:0] DLY_TAP5_VAL,
171+
input logic [5:0] DLY_TAP6_VAL,
172+
input logic [5:0] DLY_TAP7_VAL,
173+
input logic [5:0] DLY_TAP8_VAL,
174+
input logic [5:0] DLY_TAP9_VAL,
175+
input logic [5:0] DLY_TAP10_VAL,
176+
input logic [5:0] DLY_TAP11_VAL,
177+
input logic [5:0] DLY_TAP12_VAL,
178+
input logic [5:0] DLY_TAP13_VAL,
179+
input logic [5:0] DLY_TAP14_VAL,
180+
input logic [5:0] DLY_TAP15_VAL,
181+
input logic [5:0] DLY_TAP16_VAL,
182+
input logic [5:0] DLY_TAP17_VAL,
183+
input logic [5:0] DLY_TAP18_VAL,
184+
input logic [5:0] DLY_TAP19_VAL,
111185
input logic [4:0] DLY_ADDR,
112-
output logic [5:0] DLY_TAP_VALUE
186+
output reg [5:0] DLY_TAP_VALUE
113187
);
114188
endmodule
115189
`endcelldefine

‎sim_models/verilog/DLY_SEL_DCODER.v‎

Lines changed: 65 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -12,20 +12,76 @@ module DLY_SEL_DCODER (
1212
input DLY_ADJ, // Delay adjust input
1313
input DLY_INCDEC, // Delay increment / decrement input
1414
input [4:0] DLY_ADDR, // Input Address
15-
output reg [2:0] DLY_CNTRL[31:0] // Output Bus
15+
output reg [2:0] DLY0_CNTRL, // Output Bus
16+
output reg [2:0] DLY1_CNTRL, // Output Bus
17+
output reg [2:0] DLY2_CNTRL, // Output Bus
18+
output reg [2:0] DLY3_CNTRL, // Output Bus
19+
output reg [2:0] DLY4_CNTRL, // Output Bus
20+
output reg [2:0] DLY5_CNTRL, // Output Bus
21+
output reg [2:0] DLY6_CNTRL, // Output Bus
22+
output reg [2:0] DLY7_CNTRL, // Output Bus
23+
output reg [2:0] DLY8_CNTRL, // Output Bus
24+
output reg [2:0] DLY9_CNTRL, // Output Bus
25+
output reg [2:0] DLY10_CNTRL, // Output Bus
26+
output reg [2:0] DLY11_CNTRL, // Output Bus
27+
output reg [2:0] DLY12_CNTRL, // Output Bus
28+
output reg [2:0] DLY13_CNTRL, // Output Bus
29+
output reg [2:0] DLY14_CNTRL, // Output Bus
30+
output reg [2:0] DLY15_CNTRL, // Output Bus
31+
output reg [2:0] DLY16_CNTRL, // Output Bus
32+
output reg [2:0] DLY17_CNTRL, // Output Bus
33+
output reg [2:0] DLY18_CNTRL, // Output Bus
34+
output reg [2:0] DLY19_CNTRL // Output Bus
1635
);
1736

1837

1938
always @(*)
2039
begin
21-
for(integer i=0; i<32;i=i+1)
22-
begin
23-
DLY_CNTRL[i] = 3'b000;
24-
end
25-
if (DLY_ADDR < 5'd20)
26-
begin
27-
DLY_CNTRL[DLY_ADDR] = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
28-
end
40+
DLY0_CNTRL = 3'b000;
41+
DLY1_CNTRL = 3'b000;
42+
DLY2_CNTRL = 3'b000;
43+
DLY3_CNTRL = 3'b000;
44+
DLY4_CNTRL = 3'b000;
45+
DLY5_CNTRL = 3'b000;
46+
DLY6_CNTRL = 3'b000;
47+
DLY7_CNTRL = 3'b000;
48+
DLY8_CNTRL = 3'b000;
49+
DLY9_CNTRL = 3'b000;
50+
DLY10_CNTRL = 3'b000;
51+
DLY11_CNTRL = 3'b000;
52+
DLY12_CNTRL = 3'b000;
53+
DLY13_CNTRL = 3'b000;
54+
DLY14_CNTRL = 3'b000;
55+
DLY15_CNTRL = 3'b000;
56+
DLY16_CNTRL = 3'b000;
57+
DLY17_CNTRL = 3'b000;
58+
DLY18_CNTRL = 3'b000;
59+
DLY19_CNTRL = 3'b000;
60+
61+
case(DLY_ADDR)
62+
5'd0: DLY0_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
63+
5'd1: DLY1_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
64+
5'd2: DLY2_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
65+
5'd3: DLY3_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
66+
5'd4: DLY4_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
67+
5'd5: DLY5_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
68+
5'd6: DLY6_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
69+
5'd7: DLY7_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
70+
5'd8: DLY8_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
71+
5'd9: DLY9_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
72+
5'd10: DLY10_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
73+
5'd11: DLY11_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
74+
5'd12: DLY12_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
75+
5'd13: DLY13_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
76+
5'd14: DLY14_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
77+
5'd15: DLY15_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
78+
5'd16: DLY16_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
79+
5'd17: DLY17_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
80+
5'd18: DLY18_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
81+
5'd19: DLY19_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
82+
83+
endcase
84+
2985
end
3086

3187

‎sim_models/verilog/DLY_SEL_DECODER.v‎

Lines changed: 89 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,89 @@
1+
`timescale 1ps/1ps
2+
`celldefine
3+
//
4+
// DLY_SEL_DECODER simulation model
5+
// Address Decoder
6+
//
7+
// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved.
8+
//
9+
10+
module DLY_SEL_DECODER (
11+
input DLY_LOAD, // Delay load input
12+
input DLY_ADJ, // Delay adjust input
13+
input DLY_INCDEC, // Delay increment / decrement input
14+
input [4:0] DLY_ADDR, // Input Address
15+
output reg [2:0] DLY0_CNTRL, // Output Bus
16+
output reg [2:0] DLY1_CNTRL, // Output Bus
17+
output reg [2:0] DLY2_CNTRL, // Output Bus
18+
output reg [2:0] DLY3_CNTRL, // Output Bus
19+
output reg [2:0] DLY4_CNTRL, // Output Bus
20+
output reg [2:0] DLY5_CNTRL, // Output Bus
21+
output reg [2:0] DLY6_CNTRL, // Output Bus
22+
output reg [2:0] DLY7_CNTRL, // Output Bus
23+
output reg [2:0] DLY8_CNTRL, // Output Bus
24+
output reg [2:0] DLY9_CNTRL, // Output Bus
25+
output reg [2:0] DLY10_CNTRL, // Output Bus
26+
output reg [2:0] DLY11_CNTRL, // Output Bus
27+
output reg [2:0] DLY12_CNTRL, // Output Bus
28+
output reg [2:0] DLY13_CNTRL, // Output Bus
29+
output reg [2:0] DLY14_CNTRL, // Output Bus
30+
output reg [2:0] DLY15_CNTRL, // Output Bus
31+
output reg [2:0] DLY16_CNTRL, // Output Bus
32+
output reg [2:0] DLY17_CNTRL, // Output Bus
33+
output reg [2:0] DLY18_CNTRL, // Output Bus
34+
output reg [2:0] DLY19_CNTRL // Output Bus
35+
);
36+
37+
38+
always @(*)
39+
begin
40+
DLY0_CNTRL = 3'b000;
41+
DLY1_CNTRL = 3'b000;
42+
DLY2_CNTRL = 3'b000;
43+
DLY3_CNTRL = 3'b000;
44+
DLY4_CNTRL = 3'b000;
45+
DLY5_CNTRL = 3'b000;
46+
DLY6_CNTRL = 3'b000;
47+
DLY7_CNTRL = 3'b000;
48+
DLY8_CNTRL = 3'b000;
49+
DLY9_CNTRL = 3'b000;
50+
DLY10_CNTRL = 3'b000;
51+
DLY11_CNTRL = 3'b000;
52+
DLY12_CNTRL = 3'b000;
53+
DLY13_CNTRL = 3'b000;
54+
DLY14_CNTRL = 3'b000;
55+
DLY15_CNTRL = 3'b000;
56+
DLY16_CNTRL = 3'b000;
57+
DLY17_CNTRL = 3'b000;
58+
DLY18_CNTRL = 3'b000;
59+
DLY19_CNTRL = 3'b000;
60+
61+
case(DLY_ADDR)
62+
5'd0: DLY0_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
63+
5'd1: DLY1_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
64+
5'd2: DLY2_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
65+
5'd3: DLY3_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
66+
5'd4: DLY4_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
67+
5'd5: DLY5_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
68+
5'd6: DLY6_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
69+
5'd7: DLY7_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
70+
5'd8: DLY8_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
71+
5'd9: DLY9_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
72+
5'd10: DLY10_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
73+
5'd11: DLY11_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
74+
5'd12: DLY12_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
75+
5'd13: DLY13_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
76+
5'd14: DLY14_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
77+
5'd15: DLY15_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
78+
5'd16: DLY16_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
79+
5'd17: DLY17_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
80+
5'd18: DLY18_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
81+
5'd19: DLY19_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
82+
83+
endcase
84+
85+
end
86+
87+
88+
endmodule
89+
`endcelldefine

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