DLY_SEL_SECODER tb updated

moinijaz · moinijaz · commit 924b6f824e7b · 2024-10-07T12:42:13.000+05:00
diff --git a/sim_models/tb/DLY_SEL_DECODER_tb.v b/sim_models/tb/DLY_SEL_DECODER_tb.v
@@ -10,7 +10,7 @@ module DLY_SEL_DECODER_tb;
   reg [4:0] DLY_ADDR;
   wire [2:0] DLY_CNTRL[31:0];
 
-  DLY_SEL_DCODER  DLY_SEL_DCODER_inst (
+  DLY_SEL_DECODER  DLY_SEL_DECODER_inst (
     .DLY_LOAD(DLY_LOAD),
     .DLY_ADJ(DLY_ADJ),
     .DLY_INCDEC(DLY_INCDEC),
diff --git a/tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v b/tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v
@@ -10,7 +10,7 @@ module DLY_SEL_DECODER_tb;
   reg [4:0] DLY_ADDR;
   wire [2:0] DLY_CNTRL[31:0];
 
-  DLY_SEL_DCODER  DLY_SEL_DCODER_inst (
+  DLY_SEL_DECODER  DLY_SEL_DECODER_inst (
     .DLY_LOAD(DLY_LOAD),
     .DLY_ADJ(DLY_ADJ),
     .DLY_INCDEC(DLY_INCDEC),
