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6 files changed

+496
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lines changed

‎sim_models/tb/DLY_SEL_DECODER_tb.v‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,11 @@ module DLY_SEL_DECODER_tb;
2828
wire [2:0] DLY17_CNTRL;
2929
wire [2:0] DLY18_CNTRL;
3030
wire [2:0] DLY19_CNTRL;
31+
<<<<<<< HEAD
32+
=======
33+
34+
integer error=0;
35+
>>>>>>> 505331e58b8bc815c4d764074c09ee8d1cbe367e
3136

3237
integer error=0;
3338

‎sim_models/tb/DLY_VALUE_MUX_tb.v‎

Lines changed: 175 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -4,12 +4,51 @@ module DLY_VALUE_MUX_tb;
44
// Parameters
55

66
//Ports
7-
reg [5:0] DLY_TAP_VAL_ARRAY[19:0];
7+
reg [5:0] DLY_TAP0_VAL;
8+
reg [5:0] DLY_TAP1_VAL;
9+
reg [5:0] DLY_TAP2_VAL;
10+
reg [5:0] DLY_TAP3_VAL;
11+
reg [5:0] DLY_TAP4_VAL;
12+
reg [5:0] DLY_TAP5_VAL;
13+
reg [5:0] DLY_TAP6_VAL;
14+
reg [5:0] DLY_TAP7_VAL;
15+
reg [5:0] DLY_TAP8_VAL;
16+
reg [5:0] DLY_TAP9_VAL;
17+
reg [5:0] DLY_TAP10_VAL;
18+
reg [5:0] DLY_TAP11_VAL;
19+
reg [5:0] DLY_TAP12_VAL;
20+
reg [5:0] DLY_TAP13_VAL;
21+
reg [5:0] DLY_TAP14_VAL;
22+
reg [5:0] DLY_TAP15_VAL;
23+
reg [5:0] DLY_TAP16_VAL;
24+
reg [5:0] DLY_TAP17_VAL;
25+
reg [5:0] DLY_TAP18_VAL;
26+
reg [5:0] DLY_TAP19_VAL;
827
reg [4:0] DLY_ADDR;
928
wire [5:0] DLY_TAP_VALUE;
29+
integer error=0;
1030

1131
DLY_VALUE_MUX DLY_VALUE_MUX_inst (
12-
.DLY_TAP_VAL_ARRAY(DLY_TAP_VAL_ARRAY),
32+
.DLY_TAP0_VAL(DLY_TAP0_VAL),
33+
.DLY_TAP1_VAL(DLY_TAP1_VAL),
34+
.DLY_TAP2_VAL(DLY_TAP2_VAL),
35+
.DLY_TAP3_VAL(DLY_TAP3_VAL),
36+
.DLY_TAP4_VAL(DLY_TAP4_VAL),
37+
.DLY_TAP5_VAL(DLY_TAP5_VAL),
38+
.DLY_TAP6_VAL(DLY_TAP6_VAL),
39+
.DLY_TAP7_VAL(DLY_TAP7_VAL),
40+
.DLY_TAP8_VAL(DLY_TAP8_VAL),
41+
.DLY_TAP9_VAL(DLY_TAP9_VAL),
42+
.DLY_TAP10_VAL(DLY_TAP10_VAL),
43+
.DLY_TAP11_VAL(DLY_TAP11_VAL),
44+
.DLY_TAP12_VAL(DLY_TAP12_VAL),
45+
.DLY_TAP13_VAL(DLY_TAP13_VAL),
46+
.DLY_TAP14_VAL(DLY_TAP14_VAL),
47+
.DLY_TAP15_VAL(DLY_TAP15_VAL),
48+
.DLY_TAP16_VAL(DLY_TAP16_VAL),
49+
.DLY_TAP17_VAL(DLY_TAP17_VAL),
50+
.DLY_TAP18_VAL(DLY_TAP18_VAL),
51+
.DLY_TAP19_VAL(DLY_TAP19_VAL),
1352
.DLY_ADDR(DLY_ADDR),
1453
.DLY_TAP_VALUE(DLY_TAP_VALUE)
1554
);
@@ -18,37 +57,145 @@ module DLY_VALUE_MUX_tb;
1857
initial
1958
begin
2059
DLY_ADDR=0;
21-
for(integer i=0;i<20;i=i+1)
22-
DLY_TAP_VAL_ARRAY[i]=5'd0;
60+
DLY_TAP0_VAL = $urandom;
61+
DLY_TAP1_VAL = $urandom;
62+
DLY_TAP2_VAL = $urandom;
63+
DLY_TAP3_VAL = $urandom;
64+
DLY_TAP4_VAL = $urandom;
65+
DLY_TAP5_VAL = $urandom;
66+
DLY_TAP6_VAL = $urandom;
67+
DLY_TAP7_VAL = $urandom;
68+
DLY_TAP8_VAL = $urandom;
69+
DLY_TAP9_VAL = $urandom;
70+
DLY_TAP10_VAL = $urandom;
71+
DLY_TAP11_VAL = $urandom;
72+
DLY_TAP12_VAL = $urandom;
73+
DLY_TAP13_VAL = $urandom;
74+
DLY_TAP14_VAL = $urandom;
75+
DLY_TAP15_VAL = $urandom;
76+
DLY_TAP16_VAL = $urandom;
77+
DLY_TAP17_VAL = $urandom;
78+
DLY_TAP18_VAL = $urandom;
79+
DLY_TAP19_VAL = $urandom;
2380
#5;
24-
for(integer i=0;i<20;i=i+1)
25-
DLY_TAP_VAL_ARRAY[i]=$urandom;
26-
27-
// #1;
28-
// for(integer i=0;i<20;i=i+1)
29-
// $display("DLY_TAP_VAL_ARRAY[%0d] = %b", i, DLY_TAP_VAL_ARRAY[i]);
30-
#5;
31-
repeat(10)
81+
repeat(100)
3282
begin
33-
DLY_ADDR=$urandom;
34-
83+
DLY_ADDR = $urandom;
3584
#10;
36-
if(DLY_ADDR<20)
85+
if(DLY_ADDR===0)
86+
begin
87+
if(DLY_TAP_VALUE!==DLY_TAP0_VAL)
88+
error++;
89+
end
90+
91+
if(DLY_ADDR===1)
92+
begin
93+
if(DLY_TAP_VALUE!==DLY_TAP1_VAL)
94+
error++;
95+
end
96+
97+
if(DLY_ADDR===2)
98+
begin
99+
if(DLY_TAP_VALUE!==DLY_TAP2_VAL)
100+
error++;
101+
end
102+
if(DLY_ADDR===3)
103+
begin
104+
if(DLY_TAP_VALUE!==DLY_TAP3_VAL)
105+
error++;
106+
end
107+
if(DLY_ADDR===4)
108+
begin
109+
if(DLY_TAP_VALUE!==DLY_TAP4_VAL)
110+
error++;
111+
end
112+
if(DLY_ADDR===5)
113+
begin
114+
if(DLY_TAP_VALUE!==DLY_TAP5_VAL)
115+
error++;
116+
end
117+
if(DLY_ADDR===6)
118+
begin
119+
if(DLY_TAP_VALUE!==DLY_TAP6_VAL)
120+
error++;
121+
end
122+
if(DLY_ADDR===7)
123+
begin
124+
if(DLY_TAP_VALUE!==DLY_TAP7_VAL)
125+
error++;
126+
end
127+
if(DLY_ADDR===8)
128+
begin
129+
if(DLY_TAP_VALUE!==DLY_TAP8_VAL)
130+
error++;
131+
end
132+
if(DLY_ADDR===9)
133+
begin
134+
if(DLY_TAP_VALUE!==DLY_TAP9_VAL)
135+
error++;
136+
end
137+
if(DLY_ADDR===10)
138+
begin
139+
if(DLY_TAP_VALUE!==DLY_TAP10_VAL)
140+
error++;
141+
end
142+
if(DLY_ADDR===11)
143+
begin
144+
if(DLY_TAP_VALUE!==DLY_TAP11_VAL)
145+
error++;
146+
end
147+
if(DLY_ADDR===12)
148+
begin
149+
if(DLY_TAP_VALUE!==DLY_TAP12_VAL)
150+
error++;
151+
end
152+
if(DLY_ADDR===13)
153+
begin
154+
if(DLY_TAP_VALUE!==DLY_TAP13_VAL)
155+
error++;
156+
end
157+
if(DLY_ADDR===14)
158+
begin
159+
if(DLY_TAP_VALUE!==DLY_TAP14_VAL)
160+
error++;
161+
end
162+
if(DLY_ADDR===15)
163+
begin
164+
if(DLY_TAP_VALUE!==DLY_TAP15_VAL)
165+
error++;
166+
end
167+
if(DLY_ADDR===16)
168+
begin
169+
if(DLY_TAP_VALUE!==DLY_TAP16_VAL)
170+
error++;
171+
end
172+
if(DLY_ADDR===17)
173+
begin
174+
if(DLY_TAP_VALUE!==DLY_TAP17_VAL)
175+
error++;
176+
end
177+
if(DLY_ADDR===18)
178+
begin
179+
if(DLY_TAP_VALUE!==DLY_TAP18_VAL)
180+
error++;
181+
end
182+
if(DLY_ADDR===19)
183+
begin
184+
if(DLY_TAP_VALUE!==DLY_TAP19_VAL)
185+
error++;
186+
end
187+
if(DLY_ADDR>20)
37188
begin
38-
if(DLY_TAP_VALUE===DLY_TAP_VAL_ARRAY[DLY_ADDR])
39-
$display("Test Passed");
40-
else
41-
$display("Test Failed");
42-
end
43-
else
44-
begin
45-
if(DLY_TAP_VALUE===5'd0)
46-
$display("Test Passed");
47-
else
48-
$display("Test Failed");
189+
if(DLY_TAP_VALUE!==5'd0)
190+
error++;
49191
end
192+
50193
#100;
51194
end
195+
if(error===0)
196+
$display("Test Passed");
197+
else
198+
$display("Test Failed");
52199
#1000;
53200
$finish;
54201
end
@@ -57,4 +204,5 @@ module DLY_VALUE_MUX_tb;
57204
$dumpfile("waves.vcd");
58205
$dumpvars;
59206
end
60-
endmodule
207+
208+
endmodule

‎sim_models/verilog/DLY_SEL_DCODER.v‎

Lines changed: 89 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,89 @@
1+
`timescale 1ps/1ps
2+
`celldefine
3+
//
4+
// DLY_SEL_DCODER simulation model
5+
// Address Decoder
6+
//
7+
// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved.
8+
//
9+
10+
module DLY_SEL_DCODER (
11+
input DLY_LOAD, // Delay load input
12+
input DLY_ADJ, // Delay adjust input
13+
input DLY_INCDEC, // Delay increment / decrement input
14+
input [4:0] DLY_ADDR, // Input Address
15+
output reg [2:0] DLY0_CNTRL, // Output Bus
16+
output reg [2:0] DLY1_CNTRL, // Output Bus
17+
output reg [2:0] DLY2_CNTRL, // Output Bus
18+
output reg [2:0] DLY3_CNTRL, // Output Bus
19+
output reg [2:0] DLY4_CNTRL, // Output Bus
20+
output reg [2:0] DLY5_CNTRL, // Output Bus
21+
output reg [2:0] DLY6_CNTRL, // Output Bus
22+
output reg [2:0] DLY7_CNTRL, // Output Bus
23+
output reg [2:0] DLY8_CNTRL, // Output Bus
24+
output reg [2:0] DLY9_CNTRL, // Output Bus
25+
output reg [2:0] DLY10_CNTRL, // Output Bus
26+
output reg [2:0] DLY11_CNTRL, // Output Bus
27+
output reg [2:0] DLY12_CNTRL, // Output Bus
28+
output reg [2:0] DLY13_CNTRL, // Output Bus
29+
output reg [2:0] DLY14_CNTRL, // Output Bus
30+
output reg [2:0] DLY15_CNTRL, // Output Bus
31+
output reg [2:0] DLY16_CNTRL, // Output Bus
32+
output reg [2:0] DLY17_CNTRL, // Output Bus
33+
output reg [2:0] DLY18_CNTRL, // Output Bus
34+
output reg [2:0] DLY19_CNTRL // Output Bus
35+
);
36+
37+
38+
always @(*)
39+
begin
40+
DLY0_CNTRL = 3'b000;
41+
DLY1_CNTRL = 3'b000;
42+
DLY2_CNTRL = 3'b000;
43+
DLY3_CNTRL = 3'b000;
44+
DLY4_CNTRL = 3'b000;
45+
DLY5_CNTRL = 3'b000;
46+
DLY6_CNTRL = 3'b000;
47+
DLY7_CNTRL = 3'b000;
48+
DLY8_CNTRL = 3'b000;
49+
DLY9_CNTRL = 3'b000;
50+
DLY10_CNTRL = 3'b000;
51+
DLY11_CNTRL = 3'b000;
52+
DLY12_CNTRL = 3'b000;
53+
DLY13_CNTRL = 3'b000;
54+
DLY14_CNTRL = 3'b000;
55+
DLY15_CNTRL = 3'b000;
56+
DLY16_CNTRL = 3'b000;
57+
DLY17_CNTRL = 3'b000;
58+
DLY18_CNTRL = 3'b000;
59+
DLY19_CNTRL = 3'b000;
60+
61+
case(DLY_ADDR)
62+
5'd0: DLY0_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
63+
5'd1: DLY1_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
64+
5'd2: DLY2_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
65+
5'd3: DLY3_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
66+
5'd4: DLY4_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
67+
5'd5: DLY5_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
68+
5'd6: DLY6_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
69+
5'd7: DLY7_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
70+
5'd8: DLY8_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
71+
5'd9: DLY9_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
72+
5'd10: DLY10_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
73+
5'd11: DLY11_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
74+
5'd12: DLY12_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
75+
5'd13: DLY13_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
76+
5'd14: DLY14_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
77+
5'd15: DLY15_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
78+
5'd16: DLY16_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
79+
5'd17: DLY17_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
80+
5'd18: DLY18_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
81+
5'd19: DLY19_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
82+
83+
endcase
84+
85+
end
86+
87+
88+
endmodule
89+
`endcelldefine

‎sim_models/verilog/DLY_VALUE_MUX.v‎

Lines changed: 47 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,12 +8,56 @@
88
//
99

1010
module DLY_VALUE_MUX (
11-
input [5:0] DLY_TAP_VAL_ARRAY[19:0], // 20 Delay Tap Value Input Ports
11+
input [5:0] DLY_TAP0_VAL, // Delay Tap Value Input Port
12+
input [5:0] DLY_TAP1_VAL, // Delay Tap Value Input Port
13+
input [5:0] DLY_TAP2_VAL, // Delay Tap Value Input Port
14+
input [5:0] DLY_TAP3_VAL, // Delay Tap Value Input Port
15+
input [5:0] DLY_TAP4_VAL, // Delay Tap Value Input Port
16+
input [5:0] DLY_TAP5_VAL, // Delay Tap Value Input Port
17+
input [5:0] DLY_TAP6_VAL, // Delay Tap Value Input Port
18+
input [5:0] DLY_TAP7_VAL, // Delay Tap Value Input Port
19+
input [5:0] DLY_TAP8_VAL, // Delay Tap Value Input Port
20+
input [5:0] DLY_TAP9_VAL, // Delay Tap Value Input Port
21+
input [5:0] DLY_TAP10_VAL, // Delay Tap Value Input Port
22+
input [5:0] DLY_TAP11_VAL, // Delay Tap Value Input Port
23+
input [5:0] DLY_TAP12_VAL, // Delay Tap Value Input Port
24+
input [5:0] DLY_TAP13_VAL, // Delay Tap Value Input Port
25+
input [5:0] DLY_TAP14_VAL, // Delay Tap Value Input Port
26+
input [5:0] DLY_TAP15_VAL, // Delay Tap Value Input Port
27+
input [5:0] DLY_TAP16_VAL, // Delay Tap Value Input Port
28+
input [5:0] DLY_TAP17_VAL, // Delay Tap Value Input Port
29+
input [5:0] DLY_TAP18_VAL, // Delay Tap Value Input Port
30+
input [5:0] DLY_TAP19_VAL, // Delay Tap Value Input Port
1231
input [4:0] DLY_ADDR, // Input Address
13-
output [5:0] DLY_TAP_VALUE // Delay Tap Value Output Port
32+
output reg [5:0] DLY_TAP_VALUE // Delay Tap Value Output Port
1433
);
1534

16-
assign DLY_TAP_VALUE= (DLY_ADDR<20)?DLY_TAP_VAL_ARRAY[DLY_ADDR]:5'd0;
35+
always@(*)
36+
begin
37+
case(DLY_ADDR)
38+
5'd0: DLY_TAP_VALUE = DLY_TAP0_VAL;
39+
5'd1: DLY_TAP_VALUE = DLY_TAP1_VAL;
40+
5'd2: DLY_TAP_VALUE = DLY_TAP2_VAL;
41+
5'd3: DLY_TAP_VALUE = DLY_TAP3_VAL;
42+
5'd4: DLY_TAP_VALUE = DLY_TAP4_VAL;
43+
5'd5: DLY_TAP_VALUE = DLY_TAP5_VAL;
44+
5'd6: DLY_TAP_VALUE = DLY_TAP6_VAL;
45+
5'd7: DLY_TAP_VALUE = DLY_TAP7_VAL;
46+
5'd8: DLY_TAP_VALUE = DLY_TAP8_VAL;
47+
5'd9: DLY_TAP_VALUE = DLY_TAP9_VAL;
48+
5'd10: DLY_TAP_VALUE = DLY_TAP10_VAL;
49+
5'd11: DLY_TAP_VALUE = DLY_TAP11_VAL;
50+
5'd12: DLY_TAP_VALUE = DLY_TAP12_VAL;
51+
5'd13: DLY_TAP_VALUE = DLY_TAP13_VAL;
52+
5'd14: DLY_TAP_VALUE = DLY_TAP14_VAL;
53+
5'd15: DLY_TAP_VALUE = DLY_TAP15_VAL;
54+
5'd16: DLY_TAP_VALUE = DLY_TAP16_VAL;
55+
5'd17: DLY_TAP_VALUE = DLY_TAP17_VAL;
56+
5'd18: DLY_TAP_VALUE = DLY_TAP18_VAL;
57+
5'd19: DLY_TAP_VALUE = DLY_TAP19_VAL;
58+
default: DLY_TAP_VALUE = 5'd0;
59+
endcase
60+
end
1761

1862
endmodule
1963
`endcelldefine

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