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moinijazmoinijaz
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Merge pull request #129 from os-fpga/fail_sim_1.5.6
Added SIM change files from 1.5.6
2 parents 5369722 + 5a4aa09 commit b5df236

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6 files changed

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‎blackbox_models/cell_sim_blackbox.v‎

Lines changed: 41 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,26 @@ module DLY_SEL_DCODER (
9494
input logic DLY_ADJ,
9595
input logic DLY_INCDEC,
9696
input logic [4:0] DLY_ADDR,
97-
output reg [2:0] DLY_CNTRL[31:0]
97+
output reg [2:0] DLY0_CNTRL,
98+
output reg [2:0] DLY1_CNTRL,
99+
output reg [2:0] DLY2_CNTRL,
100+
output reg [2:0] DLY3_CNTRL,
101+
output reg [2:0] DLY4_CNTRL,
102+
output reg [2:0] DLY5_CNTRL,
103+
output reg [2:0] DLY6_CNTRL,
104+
output reg [2:0] DLY7_CNTRL,
105+
output reg [2:0] DLY8_CNTRL,
106+
output reg [2:0] DLY9_CNTRL,
107+
output reg [2:0] DLY10_CNTRL,
108+
output reg [2:0] DLY11_CNTRL,
109+
output reg [2:0] DLY12_CNTRL,
110+
output reg [2:0] DLY13_CNTRL,
111+
output reg [2:0] DLY14_CNTRL,
112+
output reg [2:0] DLY15_CNTRL,
113+
output reg [2:0] DLY16_CNTRL,
114+
output reg [2:0] DLY17_CNTRL,
115+
output reg [2:0] DLY18_CNTRL,
116+
output reg [2:0] DLY19_CNTRL
98117
);
99118
endmodule
100119
`endcelldefine
@@ -107,9 +126,28 @@ endmodule
107126
`celldefine
108127
(* blackbox *)
109128
module DLY_VALUE_MUX (
110-
input logic [5:0] DLY_TAP_VAL_ARRAY[19:0],
129+
input logic [5:0] DLY_TAP0_VAL,
130+
input logic [5:0] DLY_TAP1_VAL,
131+
input logic [5:0] DLY_TAP2_VAL,
132+
input logic [5:0] DLY_TAP3_VAL,
133+
input logic [5:0] DLY_TAP4_VAL,
134+
input logic [5:0] DLY_TAP5_VAL,
135+
input logic [5:0] DLY_TAP6_VAL,
136+
input logic [5:0] DLY_TAP7_VAL,
137+
input logic [5:0] DLY_TAP8_VAL,
138+
input logic [5:0] DLY_TAP9_VAL,
139+
input logic [5:0] DLY_TAP10_VAL,
140+
input logic [5:0] DLY_TAP11_VAL,
141+
input logic [5:0] DLY_TAP12_VAL,
142+
input logic [5:0] DLY_TAP13_VAL,
143+
input logic [5:0] DLY_TAP14_VAL,
144+
input logic [5:0] DLY_TAP15_VAL,
145+
input logic [5:0] DLY_TAP16_VAL,
146+
input logic [5:0] DLY_TAP17_VAL,
147+
input logic [5:0] DLY_TAP18_VAL,
148+
input logic [5:0] DLY_TAP19_VAL,
111149
input logic [4:0] DLY_ADDR,
112-
output logic [5:0] DLY_TAP_VALUE
150+
output reg [5:0] DLY_TAP_VALUE
113151
);
114152
endmodule
115153
`endcelldefine

‎sim_models/tb/DLY_SEL_DECODER_tb.v‎

Lines changed: 176 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -4,62 +4,191 @@ module DLY_SEL_DCODER_tb;
44
// Parameters
55

66
//Ports
7-
reg DLY_LOAD;
8-
reg DLY_ADJ;
9-
reg DLY_INCDEC;
7+
reg DLY_LOAD;
8+
reg DLY_ADJ;
9+
reg DLY_INCDEC;
1010
reg [4:0] DLY_ADDR;
11-
wire [2:0] DLY_CNTRL[31:0];
11+
wire [2:0] DLY0_CNTRL;
12+
wire [2:0] DLY1_CNTRL;
13+
wire [2:0] DLY2_CNTRL;
14+
wire [2:0] DLY3_CNTRL;
15+
wire [2:0] DLY4_CNTRL;
16+
wire [2:0] DLY5_CNTRL;
17+
wire [2:0] DLY6_CNTRL;
18+
wire [2:0] DLY7_CNTRL;
19+
wire [2:0] DLY8_CNTRL;
20+
wire [2:0] DLY9_CNTRL;
21+
wire [2:0] DLY10_CNTRL;
22+
wire [2:0] DLY11_CNTRL;
23+
wire [2:0] DLY12_CNTRL;
24+
wire [2:0] DLY13_CNTRL;
25+
wire [2:0] DLY14_CNTRL;
26+
wire [2:0] DLY15_CNTRL;
27+
wire [2:0] DLY16_CNTRL;
28+
wire [2:0] DLY17_CNTRL;
29+
wire [2:0] DLY18_CNTRL;
30+
wire [2:0] DLY19_CNTRL;
31+
32+
integer error=0;
1233

1334
DLY_SEL_DCODER DLY_SEL_DCODER_inst (
1435
.DLY_LOAD(DLY_LOAD),
1536
.DLY_ADJ(DLY_ADJ),
1637
.DLY_INCDEC(DLY_INCDEC),
1738
.DLY_ADDR(DLY_ADDR),
18-
.DLY_CNTRL(DLY_CNTRL)
39+
.DLY0_CNTRL(DLY0_CNTRL),
40+
.DLY1_CNTRL(DLY1_CNTRL),
41+
.DLY2_CNTRL(DLY2_CNTRL),
42+
.DLY3_CNTRL(DLY3_CNTRL),
43+
.DLY4_CNTRL(DLY4_CNTRL),
44+
.DLY5_CNTRL(DLY5_CNTRL),
45+
.DLY6_CNTRL(DLY6_CNTRL),
46+
.DLY7_CNTRL(DLY7_CNTRL),
47+
.DLY8_CNTRL(DLY8_CNTRL),
48+
.DLY9_CNTRL(DLY9_CNTRL),
49+
.DLY10_CNTRL(DLY10_CNTRL),
50+
.DLY11_CNTRL(DLY11_CNTRL),
51+
.DLY12_CNTRL(DLY12_CNTRL),
52+
.DLY13_CNTRL(DLY13_CNTRL),
53+
.DLY14_CNTRL(DLY14_CNTRL),
54+
.DLY15_CNTRL(DLY15_CNTRL),
55+
.DLY16_CNTRL(DLY16_CNTRL),
56+
.DLY17_CNTRL(DLY17_CNTRL),
57+
.DLY18_CNTRL(DLY18_CNTRL),
58+
.DLY19_CNTRL(DLY19_CNTRL)
1959
);
2060

2161

22-
initial
23-
begin
24-
DLY_LOAD=0;
25-
DLY_ADJ=0;
26-
DLY_INCDEC=0;
27-
DLY_ADDR=0;
28-
#5;
29-
repeat(5)
30-
begin
31-
DLY_LOAD=$urandom;
32-
DLY_ADJ=$urandom;
33-
DLY_INCDEC=$urandom;
34-
DLY_ADDR=$urandom;
35-
#10;
36-
// $display("Bus Array Content:");
37-
// for (integer i = 0; i < 32; i = i + 1) begin
38-
// $display("DLY_CNTRL[%0d] = %b", i, DLY_CNTRL[i]);
39-
// #2;
40-
// end
41-
if(DLY_ADDR<20)
42-
begin
43-
if(DLY_CNTRL[DLY_ADDR]==={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
44-
$display("Test Passed");
45-
else
46-
$display("Test Failed");
47-
end
48-
else
49-
begin
50-
if(DLY_CNTRL[DLY_ADDR]===3'b000)
51-
$display("Test Passed");
52-
else
53-
$display("Test Failed");
54-
end
55-
#100;
56-
end
57-
#1000;
58-
$finish;
59-
end
60-
initial
61-
begin
62+
63+
initial
64+
begin
65+
DLY_LOAD=0;
66+
DLY_ADJ=0;
67+
DLY_INCDEC=0;
68+
DLY_ADDR=0;
69+
#5;
70+
repeat(100)
71+
begin
72+
DLY_LOAD=$urandom;
73+
DLY_ADJ=$urandom;
74+
DLY_INCDEC=$urandom;
75+
DLY_ADDR=$urandom;
76+
#10;
77+
if(DLY_ADDR===0)
78+
begin
79+
if(DLY0_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
80+
error++;
81+
end
82+
83+
if(DLY_ADDR===1)
84+
begin
85+
if(DLY1_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
86+
error++;
87+
end
88+
89+
if(DLY_ADDR===2)
90+
begin
91+
if(DLY2_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
92+
error++;
93+
end
94+
if(DLY_ADDR===3)
95+
begin
96+
if(DLY3_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
97+
error++;
98+
end
99+
if(DLY_ADDR===4)
100+
begin
101+
if(DLY4_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
102+
error++;
103+
end
104+
if(DLY_ADDR===5)
105+
begin
106+
if(DLY5_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
107+
error++;
108+
end
109+
if(DLY_ADDR===6)
110+
begin
111+
if(DLY6_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
112+
error++;
113+
end
114+
if(DLY_ADDR===7)
115+
begin
116+
if(DLY7_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
117+
error++;
118+
end
119+
if(DLY_ADDR===8)
120+
begin
121+
if(DLY8_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
122+
error++;
123+
end
124+
if(DLY_ADDR===9)
125+
begin
126+
if(DLY9_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
127+
error++;
128+
end
129+
if(DLY_ADDR===10)
130+
begin
131+
if(DLY10_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
132+
error++;
133+
end
134+
if(DLY_ADDR===11)
135+
begin
136+
if(DLY11_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
137+
error++;
138+
end
139+
if(DLY_ADDR===12)
140+
begin
141+
if(DLY12_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
142+
error++;
143+
end
144+
if(DLY_ADDR===13)
145+
begin
146+
if(DLY13_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
147+
error++;
148+
end
149+
if(DLY_ADDR===14)
150+
begin
151+
if(DLY14_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
152+
error++;
153+
end
154+
if(DLY_ADDR===15)
155+
begin
156+
if(DLY15_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
157+
error++;
158+
end
159+
if(DLY_ADDR===16)
160+
begin
161+
if(DLY16_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
162+
error++;
163+
end
164+
if(DLY_ADDR===17)
165+
begin
166+
if(DLY17_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
167+
error++;
168+
end
169+
if(DLY_ADDR===18)
170+
begin
171+
if(DLY18_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
172+
error++;
173+
end
174+
if(DLY_ADDR===19)
175+
begin
176+
if(DLY19_CNTRL!=={DLY_LOAD, DLY_ADJ, DLY_INCDEC})
177+
error++;
178+
end
179+
180+
#100;
181+
end
182+
if(error===0)
183+
$display("Test Passed");
184+
else
185+
$display("Test Failed");
186+
#1000;
187+
$finish;
188+
end
189+
initial
190+
begin
62191
$dumpfile("waves.vcd");
63192
$dumpvars;
64-
end
65-
endmodule
193+
end
194+
endmodule

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