Update riscv_reg_impl.h to add warning before the assert.

[Biancaa-R]

• Solves the issue : Assertion failure when force-reading a dirty register #1309
• Added a warning message incase of force writing a dirty register.
• Helps to see which registers are inconsistent.
• Can later filter by this message if you suspect cache corruption.
• A soft indication if regs are forced before initializaton.

[Biancaa-R]

So as for the issue raised by @en-sc

The reg a0 0 / reg a0 force commands expect a fully functional RISC-V GDB server or real hardware.

Spike + remote_bitbang driver in OpenOCD is very minimal — it supports halt/resume, memory access, and basic register reads, but not all “force register write” operations reliably.

Assertion is a bug in OpenOCD, triggered by doing a force write before the register cache is valid.

• So this patch aims to send a warning in case of such an issue ,instead of abruptly stopping riscv -openocd.

[Biancaa-R]

Fix errors pointed by CI :

[en-sc]

@Biancaa-R, I believe this patch does not fix the problem, just hides the symptom.

I should have added a detailed description of the issue when creating it.
Please, take a look #1309 (comment)

[Biancaa-R]

@Biancaa-R, I believe this patch does not fix the problem, just hides the symptom.

I should have added a detailed description of the issue when creating it. Please, take a look #1309 (comment)

Sure , I'll look into it and get back .