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Enhance zve #2153
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Enhance zve #2153
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nadime15
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Two more things:
Line 101 in (isa_parser.cc) needs to be changed too:
case 'v': vlen = 128; elen = 64; zvf = true; zvd = true; zve = true;
Note: If Zve32x is supported then Zvkb or Zvbb provide support for EEW of 8, 16, and 32. If Zve64x is
supported then Zvkb or Zvbb also add support for EEW 64All of the other Vector Crypto Extensions depend on
I have not checked whether Spike currently respects this, but the vector crypto extensions can be enabled via Zve32x and Zve64x.
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By the way, we had a similar PR recently for the Sail RISC-V Model (see riscv/sail-riscv#1170) that addressed all these cases, including Vector Crypto. It might be helpful, at least for cross-checking. |
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The v extension is a superset of Zve64d. If Zve64d sets zve = true, then v should too. Currently, enabling only v leaves zve as false but zvf and zvd true, which seems inconsistent.
Yes, you are right. It is not mentioned in the Zve section, but it appears in the vector crypto section.
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Since this is an internal implementation detail, we don't really need to adhere to the principle that V is a superset of Zve, as long as users of Spike can't tell the difference. With that said, I agree this approach makes the code a bit confusing. @chihminchao did you consider doing this the other way around: like, in |
It is reasonable and let me check again |
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Cool, ping me when it's time to re-review. |
Based on spec
section 18.4
"The Zvfhmin extension depends on the Zve32f extension."
section 18.5,
"The Zvfh extension depends on the Zve32f and Zfhmin extensions."
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Based on section 18.2 in spec
"All Zve* extensions support all vector integer instructions (Section
Vector Integer Arithmetic Instructions), except that the vmulh integer
multiply variants that return the high word of the product (vmulh.vv,
vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) are not
included for EEW=64 in Zve64*."
"All Zve* extensions support all vector fixed-point arithmetic
instructions (Vector Fixed-Point Arithmetic Instructions), except that
vsmul.vv and vsmul.vx are not included in EEW=64 in Zve64*"
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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aswaterman
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Yeah, I think this version is cleaner. Thanks @chihminchao (and @nadime15 for making the suggestion).
There are some part of V that don't be covered by zveXXX configuration. The patch set wants to handle