From 817a4d78009b295370c4f873ab5b69545d35577b Mon Sep 17 00:00:00 2001 From: Chih-Min Chao Date: Tue, 30 Sep 2025 23:42:47 -0700 Subject: [PATCH 1/4] zve: relax zvfhmin and zvfh Based on spec section 18.4 "The Zvfhmin extension depends on the Zve32f extension." section 18.5, "The Zvfh extension depends on the Zve32f and Zfhmin extensions." Signed-off-by: Chih-Min Chao --- riscv/csrs.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/riscv/csrs.cc b/riscv/csrs.cc index fbd914fe83..45df5d49e5 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -736,6 +736,7 @@ bool misa_csr_t::unlogged_write(const reg_t val) noexcept { const bool prev_h = old_misa & (1L << ('H' - 'A')); const reg_t new_misa = (adjusted_val & write_mask) | (old_misa & ~write_mask); const bool new_h = new_misa & (1L << ('H' - 'A')); + const bool new_v = proc->get_isa().has_any_vector(); proc->set_extension_enable(EXT_ZCA, (new_misa & (1L << ('C' - 'A'))) || !proc->get_isa().extension_enabled('C')); proc->set_extension_enable(EXT_ZCF, (new_misa & (1L << ('F' - 'A'))) && proc->extension_enabled(EXT_ZCA) && proc->get_xlen() == 32); @@ -745,8 +746,8 @@ bool misa_csr_t::unlogged_write(const reg_t val) noexcept { proc->set_extension_enable(EXT_ZCMT, proc->extension_enabled(EXT_ZCA)); proc->set_extension_enable(EXT_ZFH, new_misa & (1L << ('F' - 'A'))); proc->set_extension_enable(EXT_ZFHMIN, new_misa & (1L << ('F' - 'A'))); - proc->set_extension_enable(EXT_ZVFH, (new_misa & (1L << ('V' - 'A'))) && proc->extension_enabled(EXT_ZFHMIN)); - proc->set_extension_enable(EXT_ZVFHMIN, new_misa & (1L << ('V' - 'A'))); + proc->set_extension_enable(EXT_ZVFH, new_v && proc->get_isa().get_zvf() && proc->extension_enabled(EXT_ZFHMIN)); + proc->set_extension_enable(EXT_ZVFHMIN, new_v && proc->get_isa().get_zvf()); proc->set_extension_enable(EXT_ZAAMO, (new_misa & (1L << ('A' - 'A'))) || !proc->get_isa().extension_enabled('A')); proc->set_extension_enable(EXT_ZALRSC, (new_misa & (1L << ('A' - 'A'))) || !proc->get_isa().extension_enabled('A')); proc->set_extension_enable(EXT_ZBA, (new_misa & (1L << ('B' - 'A'))) || !proc->get_isa().extension_enabled('B')); From d1e34d021fdbb454e9744dd8602d80347b076af6 Mon Sep 17 00:00:00 2001 From: Chih-Min Chao Date: Tue, 30 Sep 2025 23:27:20 -0700 Subject: [PATCH 2/4] zve: some MUL operaiton are unavailable to zve64 Based on section 18.2 in spec "All Zve* extensions support all vector integer instructions (Section Vector Integer Arithmetic Instructions), except that the vmulh integer multiply variants that return the high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*." "All Zve* extensions support all vector fixed-point arithmetic instructions (Vector Fixed-Point Arithmetic Instructions), except that vsmul.vv and vsmul.vx are not included in EEW=64 in Zve64*" Signed-off-by: Chih-Min Chao --- riscv/insns/vmulh_vv.h | 2 ++ riscv/insns/vmulh_vx.h | 2 ++ riscv/insns/vmulhsu_vv.h | 2 ++ riscv/insns/vmulhsu_vx.h | 2 ++ riscv/insns/vmulhu_vv.h | 2 ++ riscv/insns/vmulhu_vx.h | 2 ++ riscv/insns/vsmul_vv.h | 2 ++ riscv/insns/vsmul_vx.h | 2 ++ 8 files changed, 16 insertions(+) diff --git a/riscv/insns/vmulh_vv.h b/riscv/insns/vmulh_vv.h index e861a3397a..273d3e8686 100644 --- a/riscv/insns/vmulh_vv.h +++ b/riscv/insns/vmulh_vv.h @@ -1,4 +1,6 @@ // vmulh vd, vs2, vs1 +require(p->extension_enabled('V') || P.VU.vsew < e64); + VI_VV_LOOP ({ vd = ((int128_t)vs2 * vs1) >> sew; diff --git a/riscv/insns/vmulh_vx.h b/riscv/insns/vmulh_vx.h index b6b5503674..aaf591c1b7 100644 --- a/riscv/insns/vmulh_vx.h +++ b/riscv/insns/vmulh_vx.h @@ -1,4 +1,6 @@ // vmulh vd, vs2, rs1 +require(p->extension_enabled('V') || P.VU.vsew < e64); + VI_VX_LOOP ({ vd = ((int128_t)vs2 * rs1) >> sew; diff --git a/riscv/insns/vmulhsu_vv.h b/riscv/insns/vmulhsu_vv.h index e1c0ba6052..3903d524c2 100644 --- a/riscv/insns/vmulhsu_vv.h +++ b/riscv/insns/vmulhsu_vv.h @@ -1,4 +1,6 @@ // vmulhsu.vv vd, vs2, vs1 +require(p->extension_enabled('V') || P.VU.vsew < e64); + VI_VV_SU_LOOP({ vd = ((int128_t)vs2 * (uint128_t)vs1) >> sew; }) diff --git a/riscv/insns/vmulhsu_vx.h b/riscv/insns/vmulhsu_vx.h index 4619ea896f..b8210bc375 100644 --- a/riscv/insns/vmulhsu_vx.h +++ b/riscv/insns/vmulhsu_vx.h @@ -1,4 +1,6 @@ // vmulhsu.vx vd, vs2, rs1 +require(p->extension_enabled('V') || P.VU.vsew < e64); + VI_VX_SU_LOOP({ vd = ((int128_t)vs2 * (uint128_t)rs1) >> sew; }) diff --git a/riscv/insns/vmulhu_vv.h b/riscv/insns/vmulhu_vv.h index 0ff488c3b6..5e44aec990 100644 --- a/riscv/insns/vmulhu_vv.h +++ b/riscv/insns/vmulhu_vv.h @@ -1,4 +1,6 @@ // vmulhu vd, vs2, vs1 +require(p->extension_enabled('V') || P.VU.vsew < e64); + VI_VV_ULOOP ({ vd = ((uint128_t)vs2 * vs1) >> sew; diff --git a/riscv/insns/vmulhu_vx.h b/riscv/insns/vmulhu_vx.h index 672ad32df2..35e6ed6939 100644 --- a/riscv/insns/vmulhu_vx.h +++ b/riscv/insns/vmulhu_vx.h @@ -1,4 +1,6 @@ // vmulhu vd ,vs2, rs1 +require(p->extension_enabled('V') || P.VU.vsew < e64); + VI_VX_ULOOP ({ vd = ((uint128_t)vs2 * rs1) >> sew; diff --git a/riscv/insns/vsmul_vv.h b/riscv/insns/vsmul_vv.h index c1d0a57097..bacd75738b 100644 --- a/riscv/insns/vsmul_vv.h +++ b/riscv/insns/vsmul_vv.h @@ -1,4 +1,6 @@ // vsmul.vv vd, vs2, vs1 +require(p->extension_enabled('V') || P.VU.vsew < e64); + VI_VV_LOOP ({ VRM xrm = P.VU.get_vround_mode(); diff --git a/riscv/insns/vsmul_vx.h b/riscv/insns/vsmul_vx.h index c2e531cbc1..62dfa7c4f3 100644 --- a/riscv/insns/vsmul_vx.h +++ b/riscv/insns/vsmul_vx.h @@ -1,4 +1,6 @@ // vsmul.vx vd, vs2, rs1 +require(p->extension_enabled('V') || P.VU.vsew < e64); + VI_VX_LOOP ({ VRM xrm = P.VU.get_vround_mode(); From f364814542918bf096d00b906c598f00de751e2b Mon Sep 17 00:00:00 2001 From: Chih-Min Chao Date: Tue, 21 Oct 2025 01:43:49 -0700 Subject: [PATCH 3/4] zve: correct the requirement for convension Signed-off-by: Chih-Min Chao --- riscv/insns/vfncvt_f_x_w.h | 10 +++++----- riscv/insns/vfncvt_f_xu_w.h | 10 +++++----- riscv/insns/vfncvt_rtz_x_f_w.h | 4 ++-- riscv/insns/vfncvt_rtz_xu_f_w.h | 4 ++-- riscv/insns/vfncvt_x_f_w.h | 4 ++-- riscv/insns/vfncvt_xu_f_w.h | 4 ++-- riscv/insns/vfwcvt_f_x_v.h | 4 ++-- riscv/insns/vfwcvt_f_xu_v.h | 4 ++-- riscv/insns/vfwcvt_rtz_x_f_v.h | 2 +- riscv/insns/vfwcvt_rtz_xu_f_v.h | 2 +- riscv/insns/vfwcvt_x_f_v.h | 2 +- riscv/insns/vfwcvt_xu_f_v.h | 2 +- 12 files changed, 26 insertions(+), 26 deletions(-) diff --git a/riscv/insns/vfncvt_f_x_w.h b/riscv/insns/vfncvt_f_x_w.h index 2d4a167d03..676cd3ae6f 100644 --- a/riscv/insns/vfncvt_f_x_w.h +++ b/riscv/insns/vfncvt_f_x_w.h @@ -2,9 +2,9 @@ VI_NON_ALTFMT_INSN VI_VFP_NCVT_INT_TO_FP( - { vd = i32_to_f16(vs2); }, // BODY32 - { vd = i64_to_f32(vs2); }, // BODY64 - { require_extension(EXT_ZVFH); }, // CHECK32 - { require_extension('F'); }, // CHECK64 - int // sign + { vd = i32_to_f16(vs2); }, // BODY32 + { vd = i64_to_f32(vs2); }, // BODY64 + { require_extension(EXT_ZVFH); }, // CHECK32 + { require(p->get_isa().get_zvf()); }, // CHECK64 + int // sign ) diff --git a/riscv/insns/vfncvt_f_xu_w.h b/riscv/insns/vfncvt_f_xu_w.h index 92c81ac3e2..f90d3d7e82 100644 --- a/riscv/insns/vfncvt_f_xu_w.h +++ b/riscv/insns/vfncvt_f_xu_w.h @@ -2,9 +2,9 @@ VI_NON_ALTFMT_INSN VI_VFP_NCVT_INT_TO_FP( - { vd = ui32_to_f16(vs2); }, // BODY32 - { vd = ui64_to_f32(vs2); }, // BODY64 - { require_extension(EXT_ZVFH); }, // CHECK32 - { require_extension('F'); }, // CHECK64 - uint // sign + { vd = ui32_to_f16(vs2); }, // BODY32 + { vd = ui64_to_f32(vs2); }, // BODY64 + { require_extension(EXT_ZVFH); }, // CHECK32 + { require(p->get_isa().get_zvf()); }, // CHECK64 + uint // sign ) diff --git a/riscv/insns/vfncvt_rtz_x_f_w.h b/riscv/insns/vfncvt_rtz_x_f_w.h index 82f8228704..ad9ce215b6 100644 --- a/riscv/insns/vfncvt_rtz_x_f_w.h +++ b/riscv/insns/vfncvt_rtz_x_f_w.h @@ -6,7 +6,7 @@ VI_VFP_NCVT_FP_TO_INT( { vd = f32_to_i16(vs2, softfloat_round_minMag, true); }, // BODY32 { vd = f64_to_i32(vs2, softfloat_round_minMag, true); }, // BODY64 { require_zvfbfa_or_zvfh; }, // CHECK16 - { require(p->extension_enabled('F')); }, // CHECK32 - { require(p->extension_enabled('D')); }, // CHECK64 + { require(p->get_isa().get_zvf()); }, // CHECK32 + { require(p->get_isa().get_zvd()); }, // CHECK64 int // sign ) diff --git a/riscv/insns/vfncvt_rtz_xu_f_w.h b/riscv/insns/vfncvt_rtz_xu_f_w.h index fa0c7a3e65..d258aea95b 100644 --- a/riscv/insns/vfncvt_rtz_xu_f_w.h +++ b/riscv/insns/vfncvt_rtz_xu_f_w.h @@ -6,7 +6,7 @@ VI_VFP_NCVT_FP_TO_INT( { vd = f32_to_ui16(vs2, softfloat_round_minMag, true); }, // BODY32 { vd = f64_to_ui32(vs2, softfloat_round_minMag, true); }, // BODY64 { require_zvfbfa_or_zvfh; }, // CHECK16 - { require(p->extension_enabled('F')); }, // CHECK32 - { require(p->extension_enabled('D')); }, // CHECK64 + { require(p->get_isa().get_zvf()); }, // CHECK32 + { require(p->get_isa().get_zvd()); }, // CHECK64 uint // sign ) diff --git a/riscv/insns/vfncvt_x_f_w.h b/riscv/insns/vfncvt_x_f_w.h index f08b9e515a..929ae628f7 100644 --- a/riscv/insns/vfncvt_x_f_w.h +++ b/riscv/insns/vfncvt_x_f_w.h @@ -6,7 +6,7 @@ VI_VFP_NCVT_FP_TO_INT( { vd = f32_to_i16(vs2, softfloat_roundingMode, true); }, // BODY32 { vd = f64_to_i32(vs2, softfloat_roundingMode, true); }, // BODY64 { require_zvfbfa_or_zvfh; }, // CHECK16 - { require(p->extension_enabled('F')); }, // CHECK32 - { require(p->extension_enabled('D')); }, // CHECK64 + { require(p->get_isa().get_zvf()); }, // CHECK32 + { require(p->get_isa().get_zvd()); }, // CHECK64 int // sign ) diff --git a/riscv/insns/vfncvt_xu_f_w.h b/riscv/insns/vfncvt_xu_f_w.h index 1d5ff46160..c56bb53a07 100644 --- a/riscv/insns/vfncvt_xu_f_w.h +++ b/riscv/insns/vfncvt_xu_f_w.h @@ -6,7 +6,7 @@ VI_VFP_NCVT_FP_TO_INT( { vd = f32_to_ui16(vs2, softfloat_roundingMode, true); }, // BODY32 { vd = f64_to_ui32(vs2, softfloat_roundingMode, true); }, // BODY64 { require_zvfbfa_or_zvfh; }, // CHECK16 - { require(p->extension_enabled('F')); }, // CHECK32 - { require(p->extension_enabled('D')); }, // CHECK64 + { require(p->get_isa().get_zvf()); }, // CHECK32 + { require(p->get_isa().get_zvd()); }, // CHECK64 uint // sign ) diff --git a/riscv/insns/vfwcvt_f_x_v.h b/riscv/insns/vfwcvt_f_x_v.h index a30029e160..76a069659b 100644 --- a/riscv/insns/vfwcvt_f_x_v.h +++ b/riscv/insns/vfwcvt_f_x_v.h @@ -5,7 +5,7 @@ VI_VFP_WCVT_INT_TO_FP( { vd = i32_to_f32(vs2); }, // BODY16 { vd = i32_to_f64(vs2); }, // BODY32 { require_zvfbfa_or_zvfh; }, // CHECK8 - { require_extension('F'); }, // CHECK16 - { require_extension('D'); }, // CHECK32 + { require(p->get_isa().get_zvf()); }, // CHECK64 + { require(p->get_isa().get_zvd()); }, // CHECK64 int // sign ) diff --git a/riscv/insns/vfwcvt_f_xu_v.h b/riscv/insns/vfwcvt_f_xu_v.h index 4fbbd80d1c..f32206840b 100644 --- a/riscv/insns/vfwcvt_f_xu_v.h +++ b/riscv/insns/vfwcvt_f_xu_v.h @@ -5,7 +5,7 @@ VI_VFP_WCVT_INT_TO_FP( { vd = ui32_to_f32(vs2); }, // BODY16 { vd = ui32_to_f64(vs2); }, // BODY32 { require_zvfbfa_or_zvfh; }, // CHECK8 - { require_extension('F'); }, // CHECK16 - { require_extension('D'); }, // CHECK32 + { require(p->get_isa().get_zvf()); }, // CHECK32 + { require(p->get_isa().get_zvd()); }, // CHECK64 uint // sign ) diff --git a/riscv/insns/vfwcvt_rtz_x_f_v.h b/riscv/insns/vfwcvt_rtz_x_f_v.h index f6d2301c9c..3ed454b9f3 100644 --- a/riscv/insns/vfwcvt_rtz_x_f_v.h +++ b/riscv/insns/vfwcvt_rtz_x_f_v.h @@ -5,6 +5,6 @@ VI_VFP_WCVT_FP_TO_INT( { vd = f16_to_i32(vs2, softfloat_round_minMag, true); }, // BODY16 { vd = f32_to_i64(vs2, softfloat_round_minMag, true); }, // BODY32 { require_extension(EXT_ZVFH); }, // CHECK16 - { require_extension('F'); }, // CHECK32 + { require(p->get_isa().get_zvf()); }, // CHECK32 int // sign ) diff --git a/riscv/insns/vfwcvt_rtz_xu_f_v.h b/riscv/insns/vfwcvt_rtz_xu_f_v.h index 8e66ceff38..e0c737cbd4 100644 --- a/riscv/insns/vfwcvt_rtz_xu_f_v.h +++ b/riscv/insns/vfwcvt_rtz_xu_f_v.h @@ -5,6 +5,6 @@ VI_VFP_WCVT_FP_TO_INT( { vd = f16_to_ui32(vs2, softfloat_round_minMag, true); }, // BODY16 { vd = f32_to_ui64(vs2, softfloat_round_minMag, true); }, // BODY32 { require_extension(EXT_ZVFH); }, // CHECK16 - { require_extension('F'); }, // CHECK32 + { require(p->get_isa().get_zvf()); }, // CHECK32 uint // sign ) diff --git a/riscv/insns/vfwcvt_x_f_v.h b/riscv/insns/vfwcvt_x_f_v.h index 49a07b9355..b974c86d04 100644 --- a/riscv/insns/vfwcvt_x_f_v.h +++ b/riscv/insns/vfwcvt_x_f_v.h @@ -5,6 +5,6 @@ VI_VFP_WCVT_FP_TO_INT( { vd = f16_to_i32(vs2, softfloat_roundingMode, true); }, // BODY16 { vd = f32_to_i64(vs2, softfloat_roundingMode, true); }, // BODY32 { require_extension(EXT_ZVFH); }, // CHECK16 - { require_extension('F'); }, // CHECK32 + { require(p->get_isa().get_zvf()); }, // CHECK32 int // sign ) diff --git a/riscv/insns/vfwcvt_xu_f_v.h b/riscv/insns/vfwcvt_xu_f_v.h index 8b1a07ab35..7cf0dab1ba 100644 --- a/riscv/insns/vfwcvt_xu_f_v.h +++ b/riscv/insns/vfwcvt_xu_f_v.h @@ -5,6 +5,6 @@ VI_VFP_WCVT_FP_TO_INT( { vd = f16_to_ui32(vs2, softfloat_roundingMode, true); }, // BODY16 { vd = f32_to_ui64(vs2, softfloat_roundingMode, true); }, // BODY32 { require_extension(EXT_ZVFH); }, // CHECK16 - { require_extension('F'); }, // CHECK32 + { require(p->get_isa().get_zvf()); }, // CHECK32 uint // sign ) From b59f916de9e281d626d0b17cec8ee06a1ceaa9ba Mon Sep 17 00:00:00 2001 From: Chih-Min Chao Date: Mon, 17 Nov 2025 01:09:46 -0800 Subject: [PATCH 4/4] zve: correct the constraint for widening and floating configuraiton Signed-off-by: Chih-Min Chao --- riscv/v_ext_macros.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index d6dfe7f130..7f5256c26b 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -1790,8 +1790,15 @@ VI_VX_ULOOP({ \ }; \ VI_VFP_LOOP_CMP_END \ +#define VI_CHECK_VFP_WIDE \ + if (P.VU.vsew == e16) \ + require(p->get_isa().get_zvf()); \ + else if (P.VU.vsew == e32) \ + require(p->get_isa().get_zvd()); \ + #define VI_VFP_VF_LOOP_WIDE(BODY16, BODY32) \ VI_CHECK_DSS(false); \ + VI_CHECK_VFP_WIDE \ VI_VFP_LOOP_BASE \ switch (P.VU.vsew) { \ case e16: { \ @@ -1841,6 +1848,7 @@ VI_VX_ULOOP({ \ #define VI_VFP_VV_LOOP_WIDE(BODY16, BODY32) \ VI_CHECK_DSS(true); \ + VI_CHECK_VFP_WIDE \ VI_VFP_LOOP_BASE \ switch (P.VU.vsew) { \ case e16: { \ @@ -1890,6 +1898,7 @@ VI_VX_ULOOP({ \ #define VI_VFP_WF_LOOP_WIDE(BODY16, BODY32) \ VI_CHECK_DDS(false); \ + VI_CHECK_VFP_WIDE \ VI_VFP_LOOP_BASE \ switch (P.VU.vsew) { \ case e16: { \ @@ -1918,6 +1927,7 @@ VI_VX_ULOOP({ \ #define VI_VFP_WV_LOOP_WIDE(BODY16, BODY32) \ VI_CHECK_DDS(true); \ + VI_CHECK_VFP_WIDE \ VI_VFP_LOOP_BASE \ switch (P.VU.vsew) { \ case e16: { \