From c7ff5c78bb872b3e327960fd70325479496c953b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=87a=C4=9Fatay=20Yi=C4=9Fit=20=C5=9Eahin?= Date: Thu, 20 Nov 2025 17:50:39 +0100 Subject: [PATCH] fix: write compliant bit pattern for BAR sizing According to the PCI spec [1], "[t]o determine how much address space a Function requires, system software should write a value of all 1's to each BAR register and then read the value back." QEMU (and possibly others) mask the provided address based on the size of the address space [2], which is always larger than 128 bytes for memory BARs, so the value of the last nibble has no effect. However, cloud-hypervisor (with possibly others) is more strict in its interpretation of the specification and check for exactly the all-bits-set pattern [3]. On the latter platforms, the current pattern can be erroneously interpreted as a BAR relocation instead of sizing. [1]: PCI Express Base Specification Revision 6.0, page 930 [2]: v10.1.2:hw/pci/pci.c:1658 [3]: v49.0:pci/src/configuration.rs:979 --- src/lib.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/lib.rs b/src/lib.rs index b8c9392..3f56084 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -321,7 +321,7 @@ impl EndpointHeader { match bar.get_bits(1..3) { 0b00 => { let size = unsafe { - access.write(self.0, offset, 0xfffffff0); + access.write(self.0, offset, 0xffffffff); let mut readback = access.read(self.0, offset); access.write(self.0, offset, address); @@ -349,7 +349,7 @@ impl EndpointHeader { let address_upper = unsafe { access.read(self.0, offset + 4) }; let size = unsafe { - access.write(self.0, offset, 0xfffffff0); + access.write(self.0, offset, 0xffffffff); access.write(self.0, offset + 4, 0xffffffff); let mut readback_low = access.read(self.0, offset); let readback_high = access.read(self.0, offset + 4);