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CHANGELOG.md
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# Changelog
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## Unreleased - ReleaseDate
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+## 0.9.1 - 2022-09-09
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### Added
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- `set_0_*` for all RW1C bits, which sets the bit to 0. This prevents the bit from being cleared on write.
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- `Default` implementations for registers without RsvdP bits, which allows avoiding a redundant read.
Cargo.toml
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[package]
name = "xhci"
-version = "0.9.0"
+version = "0.9.1"
authors = ["Hiroki Tokunaga <tokusan441@gmail.com>"]
edition = "2021"
license = "MIT OR Apache-2.0"
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