@@ -173,11 +173,16 @@ impl CFGR {
173173 let pllsrcclk = self . hse . unwrap_or ( HSI / 2 ) ;
174174
175175 let pllmul = self . sysclk . unwrap_or ( pllsrcclk) / pllsrcclk;
176- let pllmul = cmp:: min ( cmp:: max ( pllmul, 1 ) , 16 ) ;
177176
178177 let ( pllmul_bits, sysclk) = if pllmul == 1 {
179178 ( None , self . hse . unwrap_or ( HSI ) )
180179 } else {
180+ #[ cfg( not( feature = "connectivity" ) ) ]
181+ let pllmul = cmp:: min ( cmp:: max ( pllmul, 1 ) , 16 ) ;
182+
183+ #[ cfg( feature = "connectivity" ) ]
184+ let pllmul = cmp:: min ( cmp:: max ( pllmul, 4 ) , 9 ) ;
185+
181186 ( Some ( pllmul as u8 - 2 ) , pllsrcclk * pllmul)
182187 } ;
183188
@@ -242,7 +247,7 @@ impl CFGR {
242247 assert ! ( pclk2 <= 72_000_000 ) ;
243248
244249 // adjust flash wait states
245- #[ cfg( feature = "stm32f103" ) ]
250+ #[ cfg( any ( feature = "stm32f103" , feature = "connectivity" ) ) ]
246251 unsafe {
247252 acr. acr ( ) . write ( |w| {
248253 w. latency ( ) . bits ( if sysclk <= 24_000_000 {
@@ -292,7 +297,8 @@ impl CFGR {
292297 if let Some ( pllmul_bits) = pllmul_bits {
293298 // enable PLL and wait for it to be ready
294299
295- rcc. cfgr . modify ( |_, w| {
300+ #[ allow( unused_unsafe) ]
301+ rcc. cfgr . modify ( |_, w| unsafe {
296302 w. pllmul ( )
297303 . bits ( pllmul_bits)
298304 . pllsrc ( )
@@ -305,6 +311,30 @@ impl CFGR {
305311 }
306312
307313 // set prescalers and clock source
314+ #[ cfg( feature = "connectivity" ) ]
315+ rcc. cfgr . modify ( |_, w| unsafe {
316+ w. adcpre ( ) . bits ( apre_bits) ;
317+ w. ppre2 ( )
318+ . bits ( ppre2_bits)
319+ . ppre1 ( )
320+ . bits ( ppre1_bits)
321+ . hpre ( )
322+ . bits ( hpre_bits)
323+ . otgfspre ( )
324+ . bit ( usbpre)
325+ . sw ( )
326+ . bits ( if pllmul_bits. is_some ( ) {
327+ // PLL
328+ 0b10
329+ } else if self . hse . is_some ( ) {
330+ // HSE
331+ 0b1
332+ } else {
333+ // HSI
334+ 0b0
335+ } )
336+ } ) ;
337+
308338 #[ cfg( feature = "stm32f103" ) ]
309339 rcc. cfgr . modify ( |_, w| unsafe {
310340 w. adcpre ( ) . bits ( apre_bits) ;
@@ -574,7 +604,7 @@ bus! {
574604 WWDG => ( APB1 , wwdgen, wwdgrst) ,
575605}
576606
577- #[ cfg( feature = "high" ) ]
607+ #[ cfg( any ( feature = "high" , feature = "connectivity" ) ) ]
578608bus ! {
579609 SPI3 => ( APB1 , spi3en, spi3rst) ,
580610}
@@ -595,22 +625,19 @@ bus! {
595625 TIM3 => ( APB1 , tim3en, tim3rst) ,
596626}
597627
598- #[ cfg( any( feature = "stm32f100" , feature = "stm32f103" , feature = "stm32f105" , ) ) ]
628+ #[ cfg( any( feature = "stm32f100" , feature = "stm32f103" , feature = "connectivity" ) ) ]
599629bus ! {
600630 TIM1 => ( APB2 , tim1en, tim1rst) ,
601631}
602632
603- #[ cfg( any( feature = "stm32f100" , feature = "stm32f105 " , feature = "high" , ) ) ]
633+ #[ cfg( any( feature = "stm32f100" , feature = "high " , feature = "connectivity" ) ) ]
604634bus ! {
605635 TIM6 => ( APB1 , tim6en, tim6rst) ,
606636}
607637
608638#[ cfg( any(
609- all(
610- feature = "high" ,
611- any( feature = "stm32f101" , feature = "stm32f103" , feature = "stm32f107" , )
612- ) ,
613- any( feature = "stm32f100" , feature = "stm32f105" , )
639+ all( feature = "high" , any( feature = "stm32f101" , feature = "stm32f103" ) ) ,
640+ any( feature = "stm32f100" , feature = "connectivity" )
614641) ) ]
615642bus ! {
616643 TIM7 => ( APB1 , tim7en, tim7rst) ,
@@ -628,7 +655,7 @@ bus! {
628655 TIM4 => ( APB1 , tim4en, tim4rst) ,
629656}
630657
631- #[ cfg( feature = "high" ) ]
658+ #[ cfg( any ( feature = "high" , feature = "connectivity" ) ) ]
632659bus ! {
633660 TIM5 => ( APB1 , tim5en, tim5rst) ,
634661}
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