@@ -14,7 +14,7 @@ use cortex_m::asm;
1414use nb:: block;
1515
1616use cortex_m_rt:: entry;
17- use stm32f1xx_hal:: { pac, prelude:: * , serial :: Config } ;
17+ use stm32f1xx_hal:: { pac, prelude:: * } ;
1818
1919#[ entry]
2020fn main ( ) -> ! {
@@ -34,33 +34,31 @@ fn main() -> ! {
3434 let mut afio = p. AFIO . constrain ( ) ;
3535
3636 // Prepare the GPIOB peripheral
37- let mut gpiob = p. GPIOB . split ( ) ;
37+ let gpiob = p. GPIOB . split ( ) ;
3838
3939 // USART1
40- // let tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh) ;
40+ // let tx = gpioa.pa9;
4141 // let rx = gpioa.pa10;
4242
4343 // USART1
44- // let tx = gpiob.pb6.into_alternate_push_pull(&mut gpiob.crl) ;
44+ // let tx = gpiob.pb6;
4545 // let rx = gpiob.pb7;
4646
4747 // USART2
48- // let tx = gpioa.pa2.into_alternate_push_pull(&mut gpioa.crl) ;
48+ // let tx = gpioa.pa2;
4949 // let rx = gpioa.pa3;
5050
5151 // USART3
5252 // Configure pb10 as a push_pull output, this will be the tx pin
53- let tx = gpiob. pb10 . into_alternate_push_pull ( & mut gpiob . crh ) ;
53+ let tx = gpiob. pb10 ;
5454 // Take ownership over pb11
5555 let rx = gpiob. pb11 ;
5656
5757 // Set up the usart device. Take ownership over the USART register and tx/rx pins. The rest of
5858 // the registers are used to enable and configure the device.
59- let mut serial = p. USART3 . serial (
60- ( tx, rx, & mut afio. mapr ) ,
61- Config :: default ( ) . baudrate ( 9600 . bps ( ) ) ,
62- & clocks,
63- ) ;
59+ let mut serial = p
60+ . USART3
61+ . serial ( ( tx, rx, & mut afio. mapr ) , 9600 . bps ( ) , & clocks) ;
6462
6563 // Loopback test. Write `X` and wait until the write is successful.
6664 let sent = b'X' ;
0 commit comments