use &mut RCC

Author: burrbull

CHANGELOG.md

@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ## [Unreleased]
 
  - Implement `Ptr`, `Sealed`, `Steal` for generic `Periph` [#834]
+ - Use `&mut RCC` for `PER::enable/reset`
  - Unmacro `Adc` [#832]
  - Use `write` instead of `modify` to clear flags [#829]
  - Bump `stm32f4-staging` to 0.18, update other dependencies [#831]

src/rcc/f4/enable.rs

@@ -5,15 +5,15 @@ macro_rules! bus_enable {
     ($PER:ident => $bit:literal) => {
         impl Enable for crate::pac::$PER {
             #[inline(always)]
-            fn enable(rcc: &RccRB) {
+            fn enable(rcc: &mut RCC) {
                 unsafe {
                     bb::set(Self::Bus::enr(rcc), $bit);
                 }
                 // Stall the pipeline to work around erratum 2.1.13 (DM00037591)
                 cortex_m::asm::dsb();
             }
             #[inline(always)]
-            fn disable(rcc: &RccRB) {
+            fn disable(rcc: &mut RCC) {
                 unsafe {
                     bb::clear(Self::Bus::enr(rcc), $bit);
                 }
@@ -30,15 +30,15 @@ macro_rules! bus_lpenable {
     ($PER:ident => $bit:literal) => {
         impl LPEnable for crate::pac::$PER {
             #[inline(always)]
-            fn enable_in_low_power(rcc: &RccRB) {
+            fn enable_in_low_power(rcc: &mut RCC) {
                 unsafe {
                     bb::set(Self::Bus::lpenr(rcc), $bit);
                 }
                 // Stall the pipeline to work around erratum 2.1.13 (DM00037591)
                 cortex_m::asm::dsb();
             }
             #[inline(always)]
-            fn disable_in_low_power(rcc: &RccRB) {
+            fn disable_in_low_power(rcc: &mut RCC) {
                 unsafe {
                     bb::clear(Self::Bus::lpenr(rcc), $bit);
                 }
@@ -55,7 +55,7 @@ macro_rules! bus_reset {
     ($PER:ident => $bit:literal) => {
         impl Reset for crate::pac::$PER {
             #[inline(always)]
-            fn reset(rcc: &RccRB) {
+            fn reset(rcc: &mut RCC) {
                 unsafe {
                     bb::set(Self::Bus::rstr(rcc), $bit);
                     bb::clear(Self::Bus::rstr(rcc), $bit);

src/rcc/f4/mod.rs

@@ -15,10 +15,10 @@ use crate::pac::rcc::RegisterBlock as RccRB;
 #[allow(clippy::missing_safety_doc)]
 pub trait Enable: RccBus {
     /// Enables peripheral
-    fn enable(rcc: &RccRB);
+    fn enable(rcc: &mut RCC);
 
     /// Disables peripheral
-    fn disable(rcc: &RccRB);
+    fn disable(rcc: &mut RCC);
 
     /// Check if peripheral enabled
     fn is_enabled() -> bool;
@@ -33,27 +33,27 @@ pub trait Enable: RccBus {
     ///
     /// Enables peripheral. Takes access to RCC internally
     unsafe fn enable_unchecked() {
-        let rcc = &*pac::RCC::ptr();
-        Self::enable(rcc);
+        let mut rcc = pac::RCC::steal();
+        Self::enable(&mut rcc);
     }
 
     /// # Safety
     ///
     /// Disables peripheral. Takes access to RCC internally
     unsafe fn disable_unchecked() {
-        let rcc = pac::RCC::ptr();
-        Self::disable(&*rcc);
+        let mut rcc = pac::RCC::steal();
+        Self::disable(&mut rcc);
     }
 }
 
 /// Low power enable/disable peripheral
 #[allow(clippy::missing_safety_doc)]
 pub trait LPEnable: RccBus {
     /// Enables peripheral in low power mode
-    fn enable_in_low_power(rcc: &RccRB);
+    fn enable_in_low_power(rcc: &mut RCC);
 
     /// Disables peripheral in low power mode
-    fn disable_in_low_power(rcc: &RccRB);
+    fn disable_in_low_power(rcc: &mut RCC);
 
     /// Check if peripheral enabled in low power mode
     fn is_enabled_in_low_power() -> bool;
@@ -68,31 +68,31 @@ pub trait LPEnable: RccBus {
     ///
     /// Enables peripheral in low power mode. Takes access to RCC internally
     unsafe fn enable_in_low_power_unchecked() {
-        let rcc = pac::RCC::ptr();
-        Self::enable_in_low_power(&*rcc);
+        let mut rcc = pac::RCC::steal();
+        Self::enable_in_low_power(&mut rcc);
     }
 
     /// # Safety
     ///
     /// Disables peripheral in low power mode. Takes access to RCC internally
     unsafe fn disable_in_low_power_unchecked() {
-        let rcc = pac::RCC::ptr();
-        Self::disable_in_low_power(&*rcc);
+        let mut rcc = pac::RCC::steal();
+        Self::disable_in_low_power(&mut rcc);
     }
 }
 
 /// Reset peripheral
 #[allow(clippy::missing_safety_doc)]
 pub trait Reset: RccBus {
     /// Resets peripheral
-    fn reset(rcc: &RccRB);
+    fn reset(rcc: &mut RCC);
 
     /// # Safety
     ///
     /// Resets peripheral. Takes access to RCC internally
     unsafe fn reset_unchecked() {
-        let rcc = pac::RCC::ptr();
-        Self::reset(&*rcc);
+        let mut rcc = pac::RCC::steal();
+        Self::reset(&mut rcc);
     }
 }
 

src/rtc.rs

@@ -4,7 +4,7 @@
 
 use crate::bb;
 use crate::pac::rtc::{dr, tr};
-use crate::pac::{self, rcc::RegisterBlock, PWR, RCC, RTC};
+use crate::pac::{self, PWR, RCC, RTC};
 use crate::rcc::Enable;
 use core::fmt;
 use fugit::RateExtU32;
@@ -152,28 +152,28 @@ impl Rtc {
         // Enable write protect
 
         unsafe {
-            let rcc = &(*RCC::ptr());
+            let mut rcc = RCC::steal();
             // As per the sample code, unlock comes first. (Enable PWR and DBP)
-            result.unlock(rcc, pwr);
+            result.unlock(&mut rcc, pwr);
             match result.clock_source {
                 ClockSource::Lse(mode) => {
                     // If necessary, enable the LSE.
                     if rcc.bdcr().read().lserdy().bit_is_clear() {
-                        result.enable_lse(rcc, mode);
+                        result.enable_lse(&mut rcc, mode);
                     }
                     // Set clock source to LSE.
                     rcc.bdcr().modify(|_, w| w.rtcsel().lse());
                 }
                 ClockSource::Lsi => {
                     // If necessary, enable the LSE.
                     if rcc.csr().read().lsirdy().bit_is_clear() {
-                        result.enable_lsi(rcc);
+                        result.enable_lsi(&mut rcc);
                     }
                     // Set clock source to LSI.
                     rcc.bdcr().modify(|_, w| w.rtcsel().lsi());
                 }
             }
-            result.enable(rcc);
+            result.enable(&mut rcc);
         }
 
         result.modify(true, |regs| {
@@ -191,7 +191,7 @@ impl Rtc {
 
     /// Enable the low frequency external oscillator. This is the only mode currently
     /// supported, to avoid exposing the `CR` and `CRS` registers.
-    fn enable_lse(&mut self, rcc: &RegisterBlock, mode: LSEClockMode) {
+    fn enable_lse(&mut self, rcc: &mut RCC, mode: LSEClockMode) {
         unsafe {
             // Force a reset of the backup domain.
             self.backup_reset(rcc);
@@ -221,15 +221,15 @@ impl Rtc {
         Self::with_config(regs, pwr, ClockSource::Lsi, prediv_s, prediv_a)
     }
 
-    fn enable_lsi(&mut self, rcc: &RegisterBlock) {
+    fn enable_lsi(&mut self, rcc: &mut RCC) {
         // Force a reset of the backup domain.
         self.backup_reset(rcc);
         // Enable the LSI.
         rcc.csr().modify(|_, w| w.lsion().on());
         while rcc.csr().read().lsirdy().is_not_ready() {}
     }
 
-    fn unlock(&mut self, rcc: &RegisterBlock, pwr: &mut PWR) {
+    fn unlock(&mut self, rcc: &mut RCC, pwr: &mut PWR) {
         // Enable the backup interface
         // Set APB1 - Bit 28 (PWREN)
         PWR::enable(rcc);
@@ -238,7 +238,7 @@ impl Rtc {
         pwr.cr().modify(|_, w| w.dbp().set_bit());
     }
 
-    fn backup_reset(&mut self, rcc: &RegisterBlock) {
+    fn backup_reset(&mut self, rcc: &mut RCC) {
         unsafe {
             // Set BDCR - Bit 16 (BDRST)
             bb::set(rcc.bdcr(), 16);
@@ -247,7 +247,7 @@ impl Rtc {
         }
     }
 
-    fn enable(&mut self, rcc: &RegisterBlock) {
+    fn enable(&mut self, rcc: &mut RCC) {
         // Start the actual RTC.
         // Set BDCR - Bit 15 (RTCEN)
         unsafe {