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use &mut RCC
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-242
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8 files changed

+237
-242
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‎CHANGELOG.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
88
## [Unreleased]
99

1010
- Implement `Ptr`, `Sealed`, `Steal` for generic `Periph` [#834]
11+
- Use `&mut RCC` for `PER::enable/reset`
1112
- Unmacro `Adc` [#832]
1213
- Use `write` instead of `modify` to clear flags [#829]
1314
- Bump `stm32f4-staging` to 0.18, update other dependencies [#831]

‎src/adc.rs‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -532,16 +532,15 @@ impl<ADC: Instance> Adc<ADC> {
532532

533533
//Set the sample time for the channel
534534
let st = sample_time as u8;
535-
let ch = channel as u8;
536535
match channel {
537536
0..=9 => self
538537
.adc_reg
539538
.smpr2()
540-
.modify(|_, w| unsafe { w.smp(ch).bits(st) }),
539+
.modify(|_, w| unsafe { w.smp(channel).bits(st) }),
541540
10..=18 => self
542541
.adc_reg
543542
.smpr1()
544-
.modify(|_, w| unsafe { w.smp(ch - 10).bits(st) }),
543+
.modify(|_, w| unsafe { w.smp(channel - 10).bits(st) }),
545544
_ => unimplemented!(),
546545
};
547546
}

‎src/fmpi2c.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -198,7 +198,7 @@ fn calculate_timing(
198198
let mut presc: u8;
199199
// if ratio is > (scll+sclh)*presc. that frequancy is not possible to generate. so
200200
// minimum frequancy possible is generated
201-
if product > 8192 as f32 {
201+
if product > 8192_f32 {
202202
// TODO: should we panic or use minimum allowed frequancy
203203
scl_l = 0x7fu8;
204204
scl_h = 0x7fu8;
@@ -214,7 +214,7 @@ fn calculate_timing(
214214
let deviation = product % tmp_presc as f32;
215215
if min_deviation > deviation {
216216
min_deviation = deviation;
217-
presc = tmp_presc as u8;
217+
presc = tmp_presc;
218218
}
219219
}
220220
// now that we have optimal prescalar value. optimal scl_l and scl_h

‎src/rcc/f4/enable.rs‎

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -5,22 +5,22 @@ macro_rules! bus_enable {
55
($PER:ident => $bit:literal) => {
66
impl Enable for crate::pac::$PER {
77
#[inline(always)]
8-
fn enable(rcc: &RccRB) {
8+
fn enable(rcc: &mut RCC) {
99
unsafe {
1010
bb::set(Self::Bus::enr(rcc), $bit);
1111
}
1212
// Stall the pipeline to work around erratum 2.1.13 (DM00037591)
1313
cortex_m::asm::dsb();
1414
}
1515
#[inline(always)]
16-
fn disable(rcc: &RccRB) {
16+
fn disable(rcc: &mut RCC) {
1717
unsafe {
1818
bb::clear(Self::Bus::enr(rcc), $bit);
1919
}
2020
}
2121
#[inline(always)]
2222
fn is_enabled() -> bool {
23-
let rcc = pac::RCC::ptr();
23+
let rcc = RCC::ptr();
2424
(Self::Bus::enr(unsafe { &*rcc }).read().bits() >> $bit) & 0x1 != 0
2525
}
2626
}
@@ -30,22 +30,22 @@ macro_rules! bus_lpenable {
3030
($PER:ident => $bit:literal) => {
3131
impl LPEnable for crate::pac::$PER {
3232
#[inline(always)]
33-
fn enable_in_low_power(rcc: &RccRB) {
33+
fn enable_in_low_power(rcc: &mut RCC) {
3434
unsafe {
3535
bb::set(Self::Bus::lpenr(rcc), $bit);
3636
}
3737
// Stall the pipeline to work around erratum 2.1.13 (DM00037591)
3838
cortex_m::asm::dsb();
3939
}
4040
#[inline(always)]
41-
fn disable_in_low_power(rcc: &RccRB) {
41+
fn disable_in_low_power(rcc: &mut RCC) {
4242
unsafe {
4343
bb::clear(Self::Bus::lpenr(rcc), $bit);
4444
}
4545
}
4646
#[inline(always)]
4747
fn is_enabled_in_low_power() -> bool {
48-
let rcc = pac::RCC::ptr();
48+
let rcc = RCC::ptr();
4949
(Self::Bus::lpenr(unsafe { &*rcc }).read().bits() >> $bit) & 0x1 != 0
5050
}
5151
}
@@ -55,10 +55,11 @@ macro_rules! bus_reset {
5555
($PER:ident => $bit:literal) => {
5656
impl Reset for crate::pac::$PER {
5757
#[inline(always)]
58-
fn reset(rcc: &RccRB) {
58+
fn reset(rcc: &mut RCC) {
59+
let rstr = Self::Bus::rstr(rcc);
5960
unsafe {
60-
bb::set(Self::Bus::rstr(rcc), $bit);
61-
bb::clear(Self::Bus::rstr(rcc), $bit);
61+
bb::set(rstr, $bit);
62+
bb::clear(rstr, $bit);
6263
}
6364
}
6465
}

‎src/rcc/f4/mod.rs‎

Lines changed: 17 additions & 215 deletions
Original file line numberDiff line numberDiff line change
@@ -1,212 +1,19 @@
11
use crate::pac::rcc::cfgr::{HPRE, SW};
2-
use crate::pac::{self, rcc, RCC};
2+
use crate::pac::RCC;
33

4-
use super::{BusClock, BusTimerClock, RccBus};
4+
use super::*;
55

66
use fugit::HertzU32 as Hertz;
77
use fugit::RateExtU32;
88

99
mod pll;
1010

1111
mod enable;
12-
use crate::pac::rcc::RegisterBlock as RccRB;
13-
14-
/// Enable/disable peripheral
15-
#[allow(clippy::missing_safety_doc)]
16-
pub trait Enable: RccBus {
17-
/// Enables peripheral
18-
fn enable(rcc: &RccRB);
19-
20-
/// Disables peripheral
21-
fn disable(rcc: &RccRB);
22-
23-
/// Check if peripheral enabled
24-
fn is_enabled() -> bool;
25-
26-
/// Check if peripheral disabled
27-
#[inline]
28-
fn is_disabled() -> bool {
29-
!Self::is_enabled()
30-
}
31-
32-
/// # Safety
33-
///
34-
/// Enables peripheral. Takes access to RCC internally
35-
unsafe fn enable_unchecked() {
36-
let rcc = &*pac::RCC::ptr();
37-
Self::enable(rcc);
38-
}
39-
40-
/// # Safety
41-
///
42-
/// Disables peripheral. Takes access to RCC internally
43-
unsafe fn disable_unchecked() {
44-
let rcc = pac::RCC::ptr();
45-
Self::disable(&*rcc);
46-
}
47-
}
48-
49-
/// Low power enable/disable peripheral
50-
#[allow(clippy::missing_safety_doc)]
51-
pub trait LPEnable: RccBus {
52-
/// Enables peripheral in low power mode
53-
fn enable_in_low_power(rcc: &RccRB);
54-
55-
/// Disables peripheral in low power mode
56-
fn disable_in_low_power(rcc: &RccRB);
57-
58-
/// Check if peripheral enabled in low power mode
59-
fn is_enabled_in_low_power() -> bool;
60-
61-
/// Check if peripheral disabled in low power mode
62-
#[inline]
63-
fn is_disabled_in_low_power() -> bool {
64-
!Self::is_enabled_in_low_power()
65-
}
66-
67-
/// # Safety
68-
///
69-
/// Enables peripheral in low power mode. Takes access to RCC internally
70-
unsafe fn enable_in_low_power_unchecked() {
71-
let rcc = pac::RCC::ptr();
72-
Self::enable_in_low_power(&*rcc);
73-
}
74-
75-
/// # Safety
76-
///
77-
/// Disables peripheral in low power mode. Takes access to RCC internally
78-
unsafe fn disable_in_low_power_unchecked() {
79-
let rcc = pac::RCC::ptr();
80-
Self::disable_in_low_power(&*rcc);
81-
}
82-
}
83-
84-
/// Reset peripheral
85-
#[allow(clippy::missing_safety_doc)]
86-
pub trait Reset: RccBus {
87-
/// Resets peripheral
88-
fn reset(rcc: &RccRB);
89-
90-
/// # Safety
91-
///
92-
/// Resets peripheral. Takes access to RCC internally
93-
unsafe fn reset_unchecked() {
94-
let rcc = pac::RCC::ptr();
95-
Self::reset(&*rcc);
96-
}
97-
}
98-
99-
/// Extension trait that constrains the `RCC` peripheral
100-
pub trait RccExt {
101-
/// Constrains the `RCC` peripheral so it plays nicely with the other abstractions
102-
fn constrain(self) -> Rcc;
103-
}
104-
105-
macro_rules! bus_struct {
106-
($( $(#[$attr:meta])* $busX:ident => ($EN:ident, $en:ident, $LPEN:ident, $lpen:ident, $RST:ident, $rst:ident, $doc:literal),)+) => {
107-
$(
108-
$(#[$attr])*
109-
#[doc = $doc]
110-
#[non_exhaustive]
111-
pub struct $busX;
112-
113-
$(#[$attr])*
114-
impl $busX {
115-
pub(crate) fn enr(rcc: &RccRB) -> &rcc::$EN {
116-
rcc.$en()
117-
}
118-
119-
pub(crate) fn lpenr(rcc: &RccRB) -> &rcc::$LPEN {
120-
rcc.$lpen()
121-
}
122-
123-
pub(crate) fn rstr(rcc: &RccRB) -> &rcc::$RST {
124-
rcc.$rst()
125-
}
126-
}
127-
)+
128-
};
129-
}
130-
131-
bus_struct! {
132-
APB1 => (APB1ENR, apb1enr, APB1LPENR, apb1lpenr, APB1RSTR, apb1rstr, "Advanced Peripheral Bus 1 (APB1) registers"),
133-
APB2 => (APB2ENR, apb2enr, APB2LPENR, apb2lpenr, APB2RSTR, apb2rstr, "Advanced Peripheral Bus 2 (APB2) registers"),
134-
AHB1 => (AHB1ENR, ahb1enr, AHB1LPENR, ahb1lpenr, AHB1RSTR, ahb1rstr, "Advanced High-performance Bus 1 (AHB1) registers"),
135-
#[cfg(not(feature = "gpio-f410"))]
136-
AHB2 => (AHB2ENR, ahb2enr, AHB2LPENR, ahb2lpenr, AHB2RSTR, ahb2rstr, "Advanced High-performance Bus 2 (AHB2) registers"),
137-
//#[cfg(any(feature = "fsmc", feature = "fmc"))]
138-
//AHB3 => (AHB3ENR, ahb3enr, AHB3LPENR, ahb3lpenr, AHB3RSTR, ahb3rstr, "Advanced High-performance Bus 3 (AHB3) registers"),
139-
}
140-
141-
/// AMBA High-performance Bus 3 (AHB3) registers
142-
#[cfg(any(feature = "fsmc", feature = "fmc"))]
143-
#[non_exhaustive]
144-
pub struct AHB3;
145-
146-
#[cfg(any(feature = "fsmc", feature = "fmc"))]
147-
impl AHB3 {
148-
#[inline(always)]
149-
fn enr(rcc: &RccRB) -> &rcc::AHB3ENR {
150-
rcc.ahb3enr()
151-
}
152-
#[cfg(feature = "fmc")]
153-
#[inline(always)]
154-
fn lpenr(rcc: &RccRB) -> &rcc::AHB3LPENR {
155-
rcc.ahb3lpenr()
156-
}
157-
#[inline(always)]
158-
fn rstr(rcc: &RccRB) -> &rcc::AHB3RSTR {
159-
rcc.ahb3rstr()
160-
}
161-
}
162-
163-
impl BusClock for AHB1 {
164-
fn clock(clocks: &Clocks) -> Hertz {
165-
clocks.hclk
166-
}
167-
}
168-
169-
#[cfg(not(feature = "gpio-f410"))]
170-
impl BusClock for AHB2 {
171-
fn clock(clocks: &Clocks) -> Hertz {
172-
clocks.hclk
173-
}
174-
}
175-
176-
#[cfg(any(feature = "fsmc", feature = "fmc"))]
177-
impl BusClock for AHB3 {
178-
fn clock(clocks: &Clocks) -> Hertz {
179-
clocks.hclk
180-
}
181-
}
182-
183-
impl BusClock for APB1 {
184-
fn clock(clocks: &Clocks) -> Hertz {
185-
clocks.pclk1
186-
}
187-
}
188-
189-
impl BusClock for APB2 {
190-
fn clock(clocks: &Clocks) -> Hertz {
191-
clocks.pclk2
192-
}
193-
}
194-
195-
impl BusTimerClock for APB1 {
196-
fn timer_clock(clocks: &Clocks) -> Hertz {
197-
clocks.timclk1
198-
}
199-
}
200-
201-
impl BusTimerClock for APB2 {
202-
fn timer_clock(clocks: &Clocks) -> Hertz {
203-
clocks.timclk2
204-
}
205-
}
20612

20713
impl RccExt for RCC {
20814
fn constrain(self) -> Rcc {
20915
Rcc {
16+
rb: self,
21017
cfgr: CFGR {
21118
hse: None,
21219
hse_bypass: false,
@@ -233,11 +40,6 @@ impl RccExt for RCC {
23340
}
23441
}
23542

236-
/// Constrained RCC peripheral
237-
pub struct Rcc {
238-
pub cfgr: CFGR,
239-
}
240-
24143
/// Built-in high speed clock frequency
24244
pub const HSI: u32 = 16_000_000; // Hz
24345

@@ -917,31 +719,31 @@ impl RealSaiClocks {
917719
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
918720
#[derive(Copy, Clone, PartialEq, Eq, Debug)]
919721
pub struct Clocks {
920-
hclk: Hertz,
921-
pclk1: Hertz,
922-
pclk2: Hertz,
923-
timclk1: Hertz,
924-
timclk2: Hertz,
925-
sysclk: Hertz,
926-
pll48clk: Option<Hertz>,
722+
pub(super) hclk: Hertz,
723+
pub(super) pclk1: Hertz,
724+
pub(super) pclk2: Hertz,
725+
pub(super) timclk1: Hertz,
726+
pub(super) timclk2: Hertz,
727+
pub(super) sysclk: Hertz,
728+
pub(super) pll48clk: Option<Hertz>,
927729

928730
#[cfg(not(feature = "rcc_i2s_apb"))]
929-
i2s_clk: Option<Hertz>,
731+
pub(super) i2s_clk: Option<Hertz>,
930732
#[cfg(feature = "rcc_i2s_apb")]
931-
i2s_apb1_clk: Option<Hertz>,
733+
pub(super) i2s_apb1_clk: Option<Hertz>,
932734
#[cfg(feature = "rcc_i2s_apb")]
933-
i2s_apb2_clk: Option<Hertz>,
735+
pub(super) i2s_apb2_clk: Option<Hertz>,
934736

935737
#[cfg(feature = "sai")]
936738
#[cfg(not(feature = "sai2"))]
937-
saia_clk: Option<Hertz>,
739+
pub(super) saia_clk: Option<Hertz>,
938740
#[cfg(feature = "sai")]
939741
#[cfg(not(feature = "sai2"))]
940-
saib_clk: Option<Hertz>,
742+
pub(super) saib_clk: Option<Hertz>,
941743
#[cfg(feature = "sai2")]
942-
sai1_clk: Option<Hertz>,
744+
pub(super) sai1_clk: Option<Hertz>,
943745
#[cfg(feature = "sai2")]
944-
sai2_clk: Option<Hertz>,
746+
pub(super) sai2_clk: Option<Hertz>,
945747
}
946748

947749
impl Clocks {

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