Merge pull request #138 from thalesfragoso/wait-pre

Wait for the new prescalers values to take effect

Author: therealprof

CHANGELOG.md

@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Changed
+
+- Wait 16 cycles after setting prescalers for some clock domains to follow manual.
+
 ## [v0.7.0] - 2020-03-07
 
 ### Changed

src/rcc.rs

@@ -353,22 +353,29 @@ impl CFGR {
             while rcc.cr.read().pllrdy().bit_is_clear() {}
         }
 
-        // Set scaling factors and select system clock source
+        // Set scaling factors
         rcc.cfgr.modify(|_, w| unsafe {
             w.ppre2()
                 .bits(ppre2_bits)
                 .ppre1()
                 .bits(ppre1_bits)
                 .hpre()
                 .variant(hpre_bits)
-                .sw()
-                .variant(if sysclk_on_pll {
-                    SW_A::PLL
-                } else if self.hse.is_some() {
-                    SW_A::HSE
-                } else {
-                    SW_A::HSI
-                })
+        });
+
+        // Wait for the new prescalers to kick in
+        // "The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after write"
+        cortex_m::asm::delay(16);
+
+        // Select system clock source
+        rcc.cfgr.modify(|_, w| {
+            w.sw().variant(if sysclk_on_pll {
+                SW_A::PLL
+            } else if self.hse.is_some() {
+                SW_A::HSE
+            } else {
+                SW_A::HSI
+            })
         });
 
         let clocks = Clocks {