loop

Author: burrbull

src/spi.rs

@@ -605,6 +605,19 @@ impl<SPI: Instance, PINS, const BIDI: bool, W, OPERATION> Spi<SPI, PINS, BIDI, W
     pub fn is_overrun(&self) -> bool {
         self.spi.sr.read().ovr().bit_is_set()
     }
+
+    fn check_errors(&self) -> Result<(), Error> {
+        let sr = self.spi.sr.read();
+        if sr.ovr().bit_is_set() {
+            Err(Error::Overrun)
+        } else if sr.modf().bit_is_set() {
+            Err(Error::ModeFault)
+        } else if sr.crcerr().bit_is_set() {
+            Err(Error::Crc)
+        } else {
+            Ok(())
+        }
+    }
 }
 
 trait ReadWriteReg<W> {
@@ -685,30 +698,47 @@ impl<SPI: Instance, PINS, const BIDI: bool, W: FrameSize, OPERATION>
     where
         WI: IntoIterator<Item = W>,
     {
-        if BIDI {
-            self.spi.cr1.modify(|_, w| w.bidioe().set_bit());
-        }
-        // Write each word when the tx buffer is empty
-        for word in words {
-            loop {
-                let sr = self.spi.sr.read();
-                if sr.txe().bit_is_set() {
-                    self.write_data_reg(word);
-                    if sr.modf().bit_is_set() {
-                        return Err(Error::ModeFault);
+        let mut words = words.into_iter();
+        if let Some(first) = words.next() {
+            if BIDI {
+                self.spi.cr1.modify(|_, w| w.bidioe().set_bit());
+            }
+            // p.2
+            self.write_data_reg(first);
+            // Write each word when the tx buffer is empty
+            // p.3,4
+            'main: loop {
+                let word = words.next();
+                let mut sr;
+                loop {
+                    sr = self.spi.sr.read();
+                    if sr.txe().bit_is_set() {
+                        if let Some(word) = word {
+                            self.write_data_reg(word);
+                            break;
+                        } else {
+                            break 'main;
+                        }
                     }
-                    break;
+                }
+                if sr.modf().bit_is_set() {
+                    self.enable(false);
+                    return Err(Error::ModeFault);
                 }
             }
+            // p.4
+            // Wait for final !BSY
+            while self.is_busy() {}
+
+            if !BIDI {
+                // Clear OVR set due to dropped received values
+                let _ = self.read_data_reg();
+            }
+            let _ = self.spi.sr.read();
+            self.check_errors()
+        } else {
+            Ok(())
         }
-        // Wait for final TXE
-        while !self.is_tx_empty() {}
-        // Wait for final !BSY
-        while self.is_busy() {}
-        // Clear OVR set due to dropped received values
-        let _ = self.read_data_reg();
-        let _ = self.spi.sr.read();
-        Ok(())
     }
 }
 

src/spi/hal_02.rs

@@ -122,7 +122,7 @@ mod blocking {
         type Error = Error;
 
         fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> {
-            self.write_iter(words.iter().copied())
+            self.spi_write(words.iter().copied())
         }
     }