Merge pull request #706 from stm32-rs/test-pac2

stm32f4-staging

Author: therealprof

.github/workflows/clippy.yml

@@ -20,5 +20,4 @@ jobs:
           key: v0.21.0
 
       - run: cargo clippy --examples --features=stm32f479,usb_fs,sdio-host,can,i2s,fsmc_lcd,rtic1
-        with:
-          token: ${{ secrets.GITHUB_TOKEN }}
+

CHANGELOG.md

@@ -7,6 +7,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Changed
+
+ - Use `stm32f4-staging` until `stm32f4` is released [#706]
+
+[#706]: https://github.com/stm32-rs/stm32f4xx-hal/pull/706
+
 ## [v0.21.0] - 2024-05-30
 
 ### Changed

Cargo.toml

@@ -33,7 +33,6 @@ cortex-m = { version = "0.7.7", features = ["critical-section-single-core"] }
 cortex-m-rt = "0.7.3"
 nb = "1.1"
 rand_core = "0.6.4"
-stm32f4 = "0.15.1"
 synopsys-usb-otg = { version = "0.4.0", features = [
     "cortex-m",
 ], optional = true }
@@ -62,6 +61,11 @@ embedded-storage = "0.3"
 vcell = "0.1.3"
 document-features = "0.2"
 
+[dependencies.stm32f4]
+package = "stm32f4-staging"
+version = "0.16.0"
+features = ["defmt", "atomics"]
+
 [dependencies.time]
 version = "0.3.14"
 default-features = false

examples/analog-stopwatch-with-spi-ssd1306.rs

@@ -65,7 +65,7 @@ enum StopwatchState {
 fn main() -> ! {
     let mut dp = pac::Peripherals::take().unwrap();
     let cp = cortex_m::peripheral::Peripherals::take().unwrap();
-    dp.RCC.apb2enr.write(|w| w.syscfgen().enabled());
+    dp.RCC.apb2enr().write(|w| w.syscfgen().enabled());
 
     let rcc = dp.RCC.constrain();
 

src/adc.rs

@@ -35,7 +35,7 @@ impl Crc32 {
     /// Reset the internal CRC32 state to the default value (0xFFFF_FFFF)
     #[inline(always)]
     pub fn init(&mut self) {
-        self.periph.cr.write(|w| w.reset().reset());
+        self.periph.cr().write(|w| w.reset().reset());
     }
 
     /// Feed words into the CRC engine.
@@ -45,10 +45,10 @@ impl Crc32 {
     pub fn update(&mut self, data: &[u32]) -> u32 {
         // Feed each word into the engine
         for word in data {
-            self.periph.dr.write(|w| w.bits(*word));
+            self.periph.dr().write(|w| w.set(*word));
         }
         // Retrieve the resulting CRC
-        self.periph.dr.read().bits()
+        self.periph.dr().read().bits()
     }
 
     /// Feed bytes into the CRC engine.
@@ -95,7 +95,7 @@ impl Crc32 {
             // Mark the scratch bytes as initialized, and then convert it to a
             // native-endian u32. Feed this into the CRC peripheral
             self.periph
-                .dr
+                .dr()
                 .write(|w| w.bits(u32::from_ne_bytes(scratch.assume_init())));
         });
 
@@ -109,11 +109,11 @@ impl Crc32 {
             // MOST significant bytes as zeroes
             scratch[..remainder.len()].copy_from_slice(remainder);
             self.periph
-                .dr
-                .write(|w| w.bits(u32::from_ne_bytes(scratch)));
+                .dr()
+                .write(|w| w.set(u32::from_ne_bytes(scratch)));
         }
 
-        self.periph.dr.read().bits()
+        self.periph.dr().read().bits()
     }
 
     /// Consume the HAL peripheral, returning the PAC peripheral

src/crc32.rs

@@ -67,19 +67,19 @@ macro_rules! dac {
         impl DacPin for $CX {
             fn enable(&mut self) {
                 let dac = unsafe { &(*DAC::ptr()) };
-                dac.cr.modify(|_, w| w.$en().set_bit());
+                dac.cr().modify(|_, w| w.$en().set_bit());
             }
         }
 
         impl DacOut<u16> for $CX {
             fn set_value(&mut self, val: u16) {
                 let dac = unsafe { &(*DAC::ptr()) };
-                dac.$dhrx.write(|w| unsafe { w.bits(val as u32) });
+                dac.$dhrx().write(|w| unsafe { w.bits(val as u32) });
             }
 
             fn get_value(&mut self) -> u16 {
                 let dac = unsafe { &(*DAC::ptr()) };
-                dac.$dac_dor.read().bits() as u16
+                dac.$dac_dor().read().bits() as u16
             }
         }
     };
@@ -101,4 +101,5 @@ impl DacExt for DAC {
 }
 
 dac!(C1, en1, cen1, cal_flag1, otrim1, mode1, dhr12r1, dor1, dacc1dhr);
+#[cfg(not(feature = "stm32f410"))]
 dac!(C2, en2, cen2, cal_flag2, otrim2, mode2, dhr12r2, dor2, dacc2dhr);

src/dac.rs

@@ -383,12 +383,12 @@ impl<DMA: Instance, const S: u8> StreamX<DMA, S> {
     #[cfg(not(any(feature = "gpio-f411", feature = "gpio-f413", feature = "gpio-f410")))]
     #[inline(always)]
     unsafe fn st() -> &'static pac::dma2::ST {
-        &(*DMA::ptr()).st[S as usize]
+        (*DMA::ptr()).st(S as usize)
     }
     #[cfg(any(feature = "gpio-f411", feature = "gpio-f413", feature = "gpio-f410"))]
     #[inline(always)]
     unsafe fn st() -> &'static pac::dma1::ST {
-        &(*DMA::ptr()).st[S as usize]
+        (*DMA::ptr()).st(S as usize)
     }
 }
 
@@ -481,183 +481,187 @@ where
     #[inline(always)]
     fn set_peripheral_address(&mut self, value: u32) {
         unsafe { Self::st() }
-            .par
+            .par()
             .write(|w| unsafe { w.pa().bits(value) });
     }
 
     #[inline(always)]
     fn set_memory_address(&mut self, value: u32) {
         unsafe { Self::st() }
-            .m0ar
+            .m0ar()
             .write(|w| unsafe { w.m0a().bits(value) });
     }
 
     #[inline(always)]
     fn memory_address(&self) -> u32 {
-        unsafe { Self::st() }.m0ar.read().m0a().bits()
+        unsafe { Self::st() }.m0ar().read().m0a().bits()
     }
 
     #[inline(always)]
     fn set_alternate_memory_address(&mut self, value: u32) {
         unsafe { Self::st() }
-            .m1ar
+            .m1ar()
             .write(|w| unsafe { w.m1a().bits(value) });
     }
 
     #[inline(always)]
     fn alternate_memory_address(&self) -> u32 {
-        unsafe { Self::st() }.m1ar.read().m1a().bits()
+        unsafe { Self::st() }.m1ar().read().m1a().bits()
     }
 
     #[inline(always)]
     fn set_number_of_transfers(&mut self, value: u16) {
-        unsafe { Self::st() }.ndtr.write(|w| w.ndt().bits(value));
+        unsafe { Self::st() }.ndtr().write(|w| w.ndt().set(value));
     }
 
     #[inline(always)]
     fn number_of_transfers(&self) -> u16 {
-        unsafe { Self::st() }.ndtr.read().ndt().bits()
+        unsafe { Self::st() }.ndtr().read().ndt().bits()
     }
 
     #[inline(always)]
     unsafe fn enable(&mut self) {
-        Self::st().cr.modify(|_, w| w.en().set_bit());
+        Self::st().cr().modify(|_, w| w.en().set_bit());
     }
 
     #[inline(always)]
     fn is_enabled(&self) -> bool {
-        unsafe { Self::st() }.cr.read().en().bit_is_set()
+        unsafe { Self::st() }.cr().read().en().bit_is_set()
     }
 
     #[inline(always)]
     unsafe fn disable(&mut self) {
-        unsafe { Self::st() }.cr.modify(|_, w| w.en().clear_bit());
+        unsafe { Self::st() }.cr().modify(|_, w| w.en().clear_bit());
     }
 
     #[inline(always)]
     fn set_channel(&mut self, channel: DmaChannel) {
         unsafe { Self::st() }
-            .cr
-            .modify(|_, w| w.chsel().bits(channel.bits()));
+            .cr()
+            .modify(|_, w| w.chsel().set(channel.bits()));
     }
 
     #[inline(always)]
     fn set_priority(&mut self, priority: config::Priority) {
         unsafe { Self::st() }
-            .cr
-            .modify(|_, w| w.pl().bits(priority.bits()));
+            .cr()
+            .modify(|_, w| w.pl().set(priority.bits()));
     }
 
     #[inline(always)]
     fn set_peripheral_increment_offset(&mut self, value: PeripheralIncrementOffset) {
         unsafe { Self::st() }
-            .cr
+            .cr()
             .modify(|_, w| w.pincos().bit(value.bits()));
     }
 
     #[inline(always)]
     unsafe fn set_memory_size(&mut self, size: DmaDataSize) {
-        Self::st().cr.modify(|_, w| w.msize().bits(size.bits()));
+        Self::st().cr().modify(|_, w| w.msize().bits(size.bits()));
     }
 
     #[inline(always)]
     unsafe fn set_peripheral_size(&mut self, size: DmaDataSize) {
-        Self::st().cr.modify(|_, w| w.psize().bits(size.bits()));
+        Self::st().cr().modify(|_, w| w.psize().bits(size.bits()));
     }
 
     #[inline(always)]
     fn set_memory_increment(&mut self, increment: bool) {
         unsafe { Self::st() }
-            .cr
+            .cr()
             .modify(|_, w| w.minc().bit(increment));
     }
 
     #[inline(always)]
     fn set_peripheral_increment(&mut self, increment: bool) {
         unsafe { Self::st() }
-            .cr
+            .cr()
             .modify(|_, w| w.pinc().bit(increment));
     }
 
     #[inline(always)]
     fn set_circular_mode(&mut self, value: bool) {
-        unsafe { Self::st() }.cr.modify(|_, w| w.circ().bit(value));
+        unsafe { Self::st() }
+            .cr()
+            .modify(|_, w| w.circ().bit(value));
     }
 
     #[inline(always)]
     fn set_direction(&mut self, direction: DmaDirection) {
         unsafe { Self::st() }
-            .cr
+            .cr()
             .modify(|_, w| unsafe { w.dir().bits(direction.bits()) });
     }
 
     #[inline(always)]
     fn set_flow_controller(&mut self, value: DmaFlowController) {
         unsafe { Self::st() }
-            .cr
+            .cr()
             .modify(|_, w| w.pfctrl().bit(value.bits()));
     }
 
     #[inline(always)]
     fn events(&self) -> BitFlags<DmaEvent> {
-        BitFlags::from_bits_truncate(unsafe { Self::st() }.cr.read().bits())
+        BitFlags::from_bits_truncate(unsafe { Self::st() }.cr().read().bits())
     }
 
     #[inline(always)]
     fn listen_fifo_error(&mut self) {
-        unsafe { Self::st() }.fcr.modify(|_, w| w.feie().set_bit());
+        unsafe { Self::st() }
+            .fcr()
+            .modify(|_, w| w.feie().set_bit());
     }
 
     #[inline(always)]
     fn unlisten_fifo_error(&mut self) {
         unsafe { Self::st() }
-            .fcr
+            .fcr()
             .modify(|_, w| w.feie().clear_bit());
     }
 
     #[inline(always)]
     fn set_double_buffer(&mut self, double_buffer: bool) {
         unsafe { Self::st() }
-            .cr
+            .cr()
             .modify(|_, w| w.dbm().bit(double_buffer));
     }
 
     #[inline(always)]
     fn set_fifo_threshold(&mut self, fifo_threshold: config::FifoThreshold) {
         unsafe { Self::st() }
-            .fcr
-            .modify(|_, w| w.fth().bits(fifo_threshold.bits()));
+            .fcr()
+            .modify(|_, w| w.fth().set(fifo_threshold.bits()));
     }
 
     #[inline(always)]
     fn set_fifo_enable(&mut self, fifo_enable: bool) {
         //Register is actually direct mode disable rather than fifo enable
         unsafe { Self::st() }
-            .fcr
+            .fcr()
             .modify(|_, w| w.dmdis().bit(fifo_enable));
     }
 
     #[inline(always)]
     fn set_memory_burst(&mut self, memory_burst: config::BurstMode) {
         unsafe { Self::st() }
-            .cr
-            .modify(|_, w| w.mburst().bits(memory_burst.bits()));
+            .cr()
+            .modify(|_, w| w.mburst().set(memory_burst.bits()));
     }
 
     #[inline(always)]
     fn set_peripheral_burst(&mut self, peripheral_burst: config::BurstMode) {
         unsafe { Self::st() }
-            .cr
-            .modify(|_, w| w.pburst().bits(peripheral_burst.bits()));
+            .cr()
+            .modify(|_, w| w.pburst().set(peripheral_burst.bits()));
     }
 
     #[inline(always)]
     fn fifo_level(&self) -> FifoLevel {
-        unsafe { Self::st() }.fcr.read().fs().bits().into()
+        unsafe { Self::st() }.fcr().read().fs().bits().into()
     }
 
     fn current_buffer(&self) -> CurrentBuffer {
-        if unsafe { Self::st() }.cr.read().ct().bit_is_set() {
+        if unsafe { Self::st() }.cr().read().ct().bit_is_set() {
             CurrentBuffer::SecondBuffer
         } else {
             CurrentBuffer::FirstBuffer
@@ -675,7 +679,7 @@ where
         enable: Option<BitFlags<DmaEvent>>,
     ) {
         unsafe {
-            Self::st().cr.modify(|r, w| {
+            Self::st().cr().modify(|r, w| {
                 w.bits({
                     let mut bits = r.bits();
                     if let Some(d) = disable {
@@ -704,7 +708,7 @@ macro_rules! dma_stream {
                 #[inline(always)]
                 fn clear_flags(&mut self, flags: impl Into<BitFlags<DmaFlag>>) {
                     let dma = unsafe { &*I::ptr() };
-                    dma.$ifcr.write(|w| unsafe { w.bits(flags.into().bits() << $isr_shift) });
+                    dma.$ifcr().write(|w| unsafe { w.bits(flags.into().bits() << $isr_shift) });
                 }
             }
 
@@ -717,7 +721,7 @@ macro_rules! dma_stream {
                     //NOTE(unsafe) Atomic read with no side effects
                     let dma = unsafe { &*I::ptr() };
                     BitFlags::from_bits_truncate(
-                        ((dma.$isr.read().bits() >> $isr_shift))
+                        ((dma.$isr().read().bits() >> $isr_shift))
                     )
                 }
             }