@@ -2,22 +2,22 @@ use core::{
22 future:: { Future , IntoFuture } ,
33 ops:: { Deref , DerefMut } ,
44 pin:: Pin ,
5- sync:: atomic:: { fence, Ordering } ,
65 task:: { Context , Poll } ,
76} ;
87
8+ use embedded_dma:: { ReadBuffer , WriteBuffer } ;
99use futures_util:: task:: AtomicWaker ;
1010
1111use crate :: interrupt;
1212use crate :: stm32:: { GPDMA1 , GPDMA2 } ;
1313
1414use super :: {
1515 ch:: {
16- Channel , ChannelRegs , DmaChannel0 , DmaChannel1 ,
17- DmaChannel2 , DmaChannel3 , DmaChannel4 , DmaChannel5 , DmaChannel6 ,
18- DmaChannel7 , DmaChannelRef ,
16+ Channel , ChannelRegs , DmaChannel0 , DmaChannel1 , DmaChannel2 ,
17+ DmaChannel3 , DmaChannel4 , DmaChannel5 , DmaChannel6 , DmaChannel7 ,
18+ DmaChannelRef ,
1919 } ,
20- DmaTransfer , Error , Instance ,
20+ DmaTransfer , Error , Instance , Word ,
2121} ;
2222
2323#[ allow( private_bounds) ]
@@ -32,65 +32,67 @@ where
3232}
3333
3434#[ allow( private_bounds) ]
35- impl < ' a , CH > IntoFuture for DmaTransfer < ' a , CH >
35+ impl < ' a , CH , S , D > IntoFuture for DmaTransfer < ' a , CH , S , D >
3636where
3737 CH : DmaChannel ,
38+ S : ReadBuffer < Word : Word > ,
39+ D : WriteBuffer < Word : Word > ,
3840{
3941 type Output = Result < ( ) , Error > ;
40- type IntoFuture = DmaTransferFuture < ' a , CH > ;
42+ type IntoFuture = DmaTransferFuture < ' a , CH , S , D > ;
4143
42- fn into_future ( self ) -> DmaTransferFuture < ' a , CH > {
44+ fn into_future ( mut self ) -> DmaTransferFuture < ' a , CH , S , D > {
4345 self . enable_interrupts ( ) ;
4446 DmaTransferFuture { transfer : self }
4547 }
4648}
4749
48- pub struct DmaTransferFuture < ' a , CH : DmaChannel > {
49- transfer : DmaTransfer < ' a , CH > ,
50+ pub struct DmaTransferFuture < ' a , CH , S , D >
51+ where
52+ CH : DmaChannel ,
53+ S : ReadBuffer < Word : Word > ,
54+ D : WriteBuffer < Word : Word > ,
55+ {
56+ transfer : DmaTransfer < ' a , CH , S , D > ,
5057}
5158
52- impl < ' a , CH > Deref for DmaTransferFuture < ' a , CH >
59+ impl < ' a , CH , S , D > Deref for DmaTransferFuture < ' a , CH , S , D >
5360where
5461 CH : DmaChannel ,
62+ S : ReadBuffer < Word : Word > ,
63+ D : WriteBuffer < Word : Word > ,
5564{
56- type Target = DmaTransfer < ' a , CH > ;
65+ type Target = DmaTransfer < ' a , CH , S , D > ;
5766
5867 fn deref ( & self ) -> & Self :: Target {
5968 & self . transfer
6069 }
6170}
6271
63- impl < ' a , CH > DerefMut for DmaTransferFuture < ' a , CH >
72+ impl < ' a , CH , S , D > DerefMut for DmaTransferFuture < ' a , CH , S , D >
6473where
6574 CH : DmaChannel ,
75+ S : ReadBuffer < Word : Word > ,
76+ D : WriteBuffer < Word : Word > ,
6677{
6778 fn deref_mut ( & mut self ) -> & mut Self :: Target {
6879 & mut self . transfer
6980 }
7081}
7182
72- impl < ' a , CH > Drop for DmaTransferFuture < ' a , CH >
83+ impl < ' a , CH , S , D > Unpin for DmaTransferFuture < ' a , CH , S , D >
7384where
7485 CH : DmaChannel ,
86+ S : ReadBuffer < Word : Word > ,
87+ D : WriteBuffer < Word : Word > ,
7588{
76- fn drop ( & mut self ) {
77- if self . is_running ( ) {
78- self . channel . abort ( ) ;
79- }
80-
81- self . disable_interrupts ( ) ;
82-
83- // Preserve the instruction and bus sequence of the preceding operation and
84- // the subsequent buffer access.
85- fence ( Ordering :: SeqCst ) ;
86- }
8789}
8890
89- impl < ' a , CH : DmaChannel > Unpin for DmaTransferFuture < ' a , CH > { }
90-
91- impl < ' a , CH > Future for DmaTransferFuture < ' a , CH >
91+ impl < ' a , CH , S , D > Future for DmaTransferFuture < ' a , CH , S , D >
9292where
9393 CH : DmaChannel + ChannelWaker ,
94+ S : ReadBuffer < Word : Word > ,
95+ D : WriteBuffer < Word : Word > ,
9496{
9597 type Output = Result < ( ) , Error > ;
9698
@@ -113,7 +115,7 @@ where
113115{
114116 #[ inline( always) ]
115117 fn handle_interrupt ( ) {
116- let ch = Self :: new ( ) ;
118+ let mut ch = Self :: new ( ) ;
117119 ch. disable_transfer_interrupts ( ) ;
118120 ch. waker ( ) . wake ( ) ;
119121 }
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