diff --git a/README.md b/README.md
index cfcbec4872..05c1aebcfa 100644
--- a/README.md
+++ b/README.md
@@ -115,6 +115,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32H563ZI | [Nucleo H563ZI](https://www.st.com/en/evaluation-tools/nucleo-h563zi.html) | *2.6.0* | |
| :green_heart: | STM32H723ZG | [Nucleo H723ZG](https://www.st.com/en/evaluation-tools/nucleo-h723zg.html) | *2.4.0* | |
| :green_heart: | STM32H743ZI | [Nucleo H743ZI(2)](https://www.st.com/en/evaluation-tools/nucleo-h743zi.html) | *1.5.0* | Nucleo H743ZI2 since 1.6.0 |
+| :yellow_heart: | STM32H745ZI-Q | [Nucleo-H745ZI-Q](https://www.st.com/en/evaluation-tools/nucleo-h745zi-q.html) | **2.12.0** | |
| :green_heart: | STM32H753ZI | [Nucleo H753ZI](https://www.st.com/en/evaluation-tools/nucleo-h753zi.html) | *2.7.0* | |
| :green_heart: | STM32H7A3ZITxQ | [NUCLEO-H7A3ZI-Q](https://www.st.com/en/evaluation-tools/nucleo-h7a3zi-q.html) | *2.10.0* | |
| :green_heart: | STM32L496ZG | [Nucleo L496ZG](http://www.st.com/en/evaluation-tools/nucleo-l496zg.html) | *1.3.0* | |
@@ -610,6 +611,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32H743XG
STM32H743XI | Generic Board | *2.7.0* | |
| :green_heart: | STM32H743ZG
STM32H743ZI | Generic Board | *2.0.0* | |
| :green_heart: | STM32H745XG
STM32H745XI | Generic Board | *2.7.0* | |
+| :yellow_heart: | STM32H745ZG
STM32H745ZI | Generic Board | **2.12.0** | |
| :green_heart: | STM32H747AG
STM32H747AI | Generic Board | *2.0.0* | |
| :green_heart: | STM32H747IG
STM32H747II | Generic Board | *2.0.0* | |
| :green_heart: | STM32H747XG
STM32H747XI | Generic Board | *2.7.0* | |
@@ -626,6 +628,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32H753XI | Generic Board | *2.7.0* | |
| :green_heart: | STM32H753ZI | Generic Board | *2.0.0* | |
| :green_heart: | STM32H755XI | Generic Board | *2.7.0* | |
+| :yellow_heart: | STM32H755ZI | Generic Board | **2.12.0** | |
| :green_heart: | STM32H757AI | Generic Board | *2.0.0* | |
| :green_heart: | STM32H757II | Generic Board | *2.0.0* | |
| :green_heart: | STM32H757XI | Generic Board | *2.7.0* | |
diff --git a/boards.txt b/boards.txt
index 3d40c56814..bda31ad9eb 100644
--- a/boards.txt
+++ b/boards.txt
@@ -257,6 +257,24 @@ Nucleo_144.menu.pnum.NUCLEO_H743ZI2.build.variant_h=variant_NUCLEO_H743ZI.h
Nucleo_144.menu.pnum.NUCLEO_H743ZI2.openocd.target=stm32h7x
Nucleo_144.menu.pnum.NUCLEO_H743ZI2.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H743.svd
+# NUCLEO_H745ZI_Q board
+Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q=Nucleo H745ZI-Q
+Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.node=NODE_H743ZIQ
+Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.upload.maximum_size=2097152
+Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.upload.maximum_data_size=884736
+Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.build.mcu=cortex-m7
+Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.build.fpu=-mfpu=fpv4-sp-d16
+Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.build.float-abi=-mfloat-abi=hard
+Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -DCORE_CM7
+Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.build.board=NUCLEO_H745ZI_Q
+Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.build.series=STM32H7xx
+Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.build.product_line=STM32H745xx
+Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.build.variant=STM32H7xx/H745Z(G-I)T_H755ZIT
+Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.build.variant_h=variant_NUCLEO_H745ZI_Q.h
+Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.openocd.target=stm32h7x
+Nucleo_144.menu.pnum.NUCLEO_H745ZI_Q.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H745_CM7.svd
+
+
# NUCLEO_H753ZI board
Nucleo_144.menu.pnum.NUCLEO_H753ZI=Nucleo H753ZI
Nucleo_144.menu.pnum.NUCLEO_H753ZI.node=NODE_H753ZI
@@ -9830,6 +9848,24 @@ GenH7.menu.pnum.GENERIC_H745XIHX.build.product_line=STM32H745xx
GenH7.menu.pnum.GENERIC_H745XIHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH
GenH7.menu.pnum.GENERIC_H745XIHX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H745_CM7.svd
+# Generic H745ZGTx
+GenH7.menu.pnum.GENERIC_H745ZGTX=Generic H745ZGTx
+GenH7.menu.pnum.GENERIC_H745ZGTX.upload.maximum_size=1048576
+GenH7.menu.pnum.GENERIC_H745ZGTX.upload.maximum_data_size=884736
+GenH7.menu.pnum.GENERIC_H745ZGTX.build.board=GENERIC_H745ZGTX
+GenH7.menu.pnum.GENERIC_H745ZGTX.build.product_line=STM32H745xG
+GenH7.menu.pnum.GENERIC_H745ZGTX.build.variant=STM32H7xx/H745Z(G-I)T_H755ZIT
+GenH7.menu.pnum.GENERIC_H745ZGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H745_CM7.svd
+
+# Generic H745ZITx
+GenH7.menu.pnum.GENERIC_H745ZITX=Generic H745ZITx
+GenH7.menu.pnum.GENERIC_H745ZITX.upload.maximum_size=2097152
+GenH7.menu.pnum.GENERIC_H745ZITX.upload.maximum_data_size=884736
+GenH7.menu.pnum.GENERIC_H745ZITX.build.board=GENERIC_H745ZITX
+GenH7.menu.pnum.GENERIC_H745ZITX.build.product_line=STM32H745xx
+GenH7.menu.pnum.GENERIC_H745ZITX.build.variant=STM32H7xx/H745Z(G-I)T_H755ZIT
+GenH7.menu.pnum.GENERIC_H745ZITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H745_CM7.svd
+
# Generic H747AGIx
GenH7.menu.pnum.GENERIC_H747AGIX=Generic H747AGIx
GenH7.menu.pnum.GENERIC_H747AGIX.upload.maximum_size=1048576
@@ -9992,6 +10028,15 @@ GenH7.menu.pnum.GENERIC_H755XIHX.build.product_line=STM32H755xx
GenH7.menu.pnum.GENERIC_H755XIHX.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH
GenH7.menu.pnum.GENERIC_H755XIHX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H755_CM7.svd
+# Generic H755ZITx
+GenH7.menu.pnum.GENERIC_H755ZITX=Generic H755ZITx
+GenH7.menu.pnum.GENERIC_H755ZITX.upload.maximum_size=2097152
+GenH7.menu.pnum.GENERIC_H755ZITX.upload.maximum_data_size=884736
+GenH7.menu.pnum.GENERIC_H755ZITX.build.board=GENERIC_H755ZITX
+GenH7.menu.pnum.GENERIC_H755ZITX.build.product_line=STM32H755xx
+GenH7.menu.pnum.GENERIC_H755ZITX.build.variant=STM32H7xx/H745Z(G-I)T_H755ZIT
+GenH7.menu.pnum.GENERIC_H755ZITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H755_CM7.svd
+
# Generic H757AIIx
GenH7.menu.pnum.GENERIC_H757AIIX=Generic H757AIIx
GenH7.menu.pnum.GENERIC_H757AIIX.upload.maximum_size=2097152
diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake
index da2276e944..a44bf0d9bb 100644
--- a/cmake/boards_db.cmake
+++ b/cmake/boards_db.cmake
@@ -81022,6 +81022,88 @@ target_compile_options(GENERIC_H745XIHX_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
+# GENERIC_H745ZITX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_H745ZITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H745Z(G-I)T_H755ZIT")
+set(GENERIC_H745ZITX_MAXSIZE 2097152)
+set(GENERIC_H745ZITX_MAXDATASIZE 884736)
+set(GENERIC_H745ZITX_MCU cortex-m7)
+set(GENERIC_H745ZITX_FPCONF "-")
+add_library(GENERIC_H745ZITX INTERFACE)
+target_compile_options(GENERIC_H745ZITX INTERFACE
+ "SHELL:-DCORE_CM7 -DSTM32H745xx"
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_H745ZITX_MCU}
+)
+target_compile_definitions(GENERIC_H745ZITX INTERFACE
+ "STM32H7xx"
+ "ARDUINO_GENERIC_H745ZITX"
+ "BOARD_NAME=\"GENERIC_H745ZITX\""
+ "BOARD_ID=GENERIC_H745ZITX"
+ "VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_H745ZITX INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/
+ ${GENERIC_H745ZITX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_H745ZITX INTERFACE
+ "LINKER:--default-script=${GENERIC_H745ZITX_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=2097152"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=884736"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${GENERIC_H745ZITX_MCU}
+)
+
+add_library(GENERIC_H745ZITX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_H745ZITX_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_H745ZITX_serial_generic INTERFACE)
+target_compile_options(GENERIC_H745ZITX_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_H745ZITX_serial_none INTERFACE)
+target_compile_options(GENERIC_H745ZITX_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_H745ZITX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_H745ZITX_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_H745ZITX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_H745ZITX_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_H745ZITX_usb_HID INTERFACE)
+target_compile_options(GENERIC_H745ZITX_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_H745ZITX_usb_none INTERFACE)
+target_compile_options(GENERIC_H745ZITX_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_H745ZITX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_H745ZITX_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(GENERIC_H745ZITX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_H745ZITX_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_H745ZITX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_H745ZITX_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
# GENERIC_H747AGIX
# -----------------------------------------------------------------------------
@@ -112956,6 +113038,88 @@ target_compile_options(NUCLEO_H743ZI2_xusb_HSFS INTERFACE
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
)
+# NUCLEO_H745ZI_Q
+# -----------------------------------------------------------------------------
+
+set(NUCLEO_H745ZI_Q_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H745Z(G-I)T_H755ZIT")
+set(NUCLEO_H745ZI_Q_MAXSIZE 2097152)
+set(NUCLEO_H745ZI_Q_MAXDATASIZE 884736)
+set(NUCLEO_H745ZI_Q_MCU cortex-m7)
+set(NUCLEO_H745ZI_Q_FPCONF "fpv4-sp-d16-hard")
+add_library(NUCLEO_H745ZI_Q INTERFACE)
+target_compile_options(NUCLEO_H745ZI_Q INTERFACE
+ "SHELL:-DSTM32H745xx -DCORE_CM7"
+ "SHELL:"
+ "SHELL:"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${NUCLEO_H745ZI_Q_MCU}
+)
+target_compile_definitions(NUCLEO_H745ZI_Q INTERFACE
+ "STM32H7xx"
+ "ARDUINO_NUCLEO_H745ZI_Q"
+ "BOARD_NAME=\"NUCLEO_H745ZI_Q\""
+ "BOARD_ID=NUCLEO_H745ZI_Q"
+ "VARIANT_H=\"variant_NUCLEO_H745ZI_Q.h\""
+)
+target_include_directories(NUCLEO_H745ZI_Q INTERFACE
+ ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/
+ ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/
+ ${NUCLEO_H745ZI_Q_VARIANT_PATH}
+)
+
+target_link_options(NUCLEO_H745ZI_Q INTERFACE
+ "LINKER:--default-script=${NUCLEO_H745ZI_Q_VARIANT_PATH}/ldscript.ld"
+ "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+ "LINKER:--defsym=LD_MAX_SIZE=2097152"
+ "LINKER:--defsym=LD_MAX_DATA_SIZE=884736"
+ "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+ -mcpu=${NUCLEO_H745ZI_Q_MCU}
+)
+
+add_library(NUCLEO_H745ZI_Q_serial_disabled INTERFACE)
+target_compile_options(NUCLEO_H745ZI_Q_serial_disabled INTERFACE
+ "SHELL:"
+)
+add_library(NUCLEO_H745ZI_Q_serial_generic INTERFACE)
+target_compile_options(NUCLEO_H745ZI_Q_serial_generic INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(NUCLEO_H745ZI_Q_serial_none INTERFACE)
+target_compile_options(NUCLEO_H745ZI_Q_serial_none INTERFACE
+ "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(NUCLEO_H745ZI_Q_usb_CDC INTERFACE)
+target_compile_options(NUCLEO_H745ZI_Q_usb_CDC INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(NUCLEO_H745ZI_Q_usb_CDCgen INTERFACE)
+target_compile_options(NUCLEO_H745ZI_Q_usb_CDCgen INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(NUCLEO_H745ZI_Q_usb_HID INTERFACE)
+target_compile_options(NUCLEO_H745ZI_Q_usb_HID INTERFACE
+ "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(NUCLEO_H745ZI_Q_usb_none INTERFACE)
+target_compile_options(NUCLEO_H745ZI_Q_usb_none INTERFACE
+ "SHELL:"
+)
+add_library(NUCLEO_H745ZI_Q_xusb_FS INTERFACE)
+target_compile_options(NUCLEO_H745ZI_Q_xusb_FS INTERFACE
+ "SHELL:"
+)
+add_library(NUCLEO_H745ZI_Q_xusb_HS INTERFACE)
+target_compile_options(NUCLEO_H745ZI_Q_xusb_HS INTERFACE
+ "SHELL:-DUSE_USB_HS"
+)
+add_library(NUCLEO_H745ZI_Q_xusb_HSFS INTERFACE)
+target_compile_options(NUCLEO_H745ZI_Q_xusb_HSFS INTERFACE
+ "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
# NUCLEO_H753ZI
# -----------------------------------------------------------------------------
diff --git a/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/CMakeLists.txt b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/CMakeLists.txt
index 2a4d55b6b1..64fd7fa8a2 100644
--- a/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/CMakeLists.txt
+++ b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/CMakeLists.txt
@@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL
generic_clock.c
PeripheralPins.c
variant_generic.cpp
+ variant_NUCLEO_H745ZI_Q.cpp
)
target_link_libraries(variant_bin PUBLIC variant_usage)
diff --git a/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/generic_clock.c b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/generic_clock.c
index 6d08710e79..f29dd793d8 100644
--- a/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/generic_clock.c
+++ b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/generic_clock.c
@@ -1,6 +1,6 @@
/*
*******************************************************************************
- * Copyright (c) 2020-2021, STMicroelectronics
+ * Copyright (c) 2020-2025, STMicroelectronics
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -21,8 +21,55 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
+
+ /** Supply configuration update enable
+ */
+ HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+
+ while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_DIV1;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
+ | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+ RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
+ RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
+
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/ldscript.ld b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/ldscript.ld
new file mode 100644
index 0000000000..e9bc5ceaa4
--- /dev/null
+++ b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/ldscript.ld
@@ -0,0 +1,176 @@
+/*
+******************************************************************************
+**
+
+** File : LinkerScript.ld
+**
+**
+** Abstract : Linker script for STM32H7 series
+** 1024Kbytes FLASH and 192Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2025 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20020000; /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+RAM (xrw) : ORIGIN = 0x20000000 , LENGTH = LD_MAX_DATA_SIZE
+ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } >FLASH
+ .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+
diff --git a/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/variant_NUCLEO_H745ZI_Q.cpp b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/variant_NUCLEO_H745ZI_Q.cpp
new file mode 100644
index 0000000000..ffe6c4a795
--- /dev/null
+++ b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/variant_NUCLEO_H745ZI_Q.cpp
@@ -0,0 +1,228 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2025, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#if defined(ARDUINO_NUCLEO_H745ZI_Q)
+#include "pins_arduino.h"
+
+// Digital PinName array
+const PinName digitalPin[] = {
+ PB_7, // 0
+ PB_6, // 1
+ PG_14, // 2
+ PE_13, // 3
+ PE_14, // 4
+ PE_11, // 5
+ PA_8, // 6
+ PG_12, // 7
+ PG_9, // 8
+ PD_15, // 9
+ PD_14, // 10
+ PB_5, // 11
+ PA_6, // 12
+ PA_5, // 13
+ PB_9, // 14
+ PB_8, // 15
+ PC_6, // 16
+ PB_15, // 17
+ PB_13, // 18
+ PB_12, // 19
+ PA_15, // 20
+ PC_7, // 21
+ PB_5, // 22
+ PB_3, // 23
+ PA_4, // 24
+ PB_4, // 25
+ PG_6, // 26
+ PB_2, // 27
+ PD_13, // 28
+ PD_12, // 29
+ PD_11, // 30
+ PE_2, // 31
+ PA_0, // 32
+ PB_0, // 33
+ PE_0, // 34
+ PB_11, // 35
+ PB_10, // 36
+ PE_15, // 37
+ PE_6, // 38
+ PE_12, // 39
+ PE_10, // 40
+ PE_7, // 41
+ PE_8, // 42
+ PC_8, // 43
+ PC_9, // 44
+ PC_10, // 45
+ PC_11, // 46
+ PC_12, // 47
+ PD_2, // 48
+ PG_10, // 49
+ PG_8, // 50
+ PD_7, // 51
+ PD_6, // 52
+ PD_5, // 53
+ PD_4, // 54
+ PD_3, // 55
+ PE_2, // 56
+ PE_4, // 57
+ PE_5, // 58
+ PE_6, // 59
+ PE_3, // 60
+ PF_8, // 61
+ PF_7, // 62
+ PF_9, // 63
+ PD_10, // 64
+ PB_14, // 65
+ PD_1, // 66
+ PD_0, // 67
+ PF_15, // 68
+ PF_14, // 69
+ PB_5, // 70
+ PE_9, // 71
+ PB_2, // 72
+ PA_13, // 73
+ PA_14, // 74
+ PC_13, // 75
+ PC_14, // 76
+ PC_15, // 77
+ PH_0, // 78
+ PH_1, // 79
+ PE_1, // 80
+ PD_9, // 81
+ PA_1, // 82
+ PC_1, // 83
+ PG_13, // 84
+ PG_11, // 85
+ PA_7, // 86
+ PA_9, // 87
+ PA_10, // 88
+ PG_7, // 89
+ PC_5, // 90
+ PD_8, // 91
+ PA_12, // 92
+ PA_11, // 93
+ PC_4, // 94
+ PA_3, // 95
+ PC_0, // 96
+ PC_3, // 97
+ PB_1, // 98
+ PC_2, // 99
+ PF_11, // 100
+ PF_6, // 101
+ PF_10, // 102
+ PA_2 // 103
+};
+
+
+// Analog (Ax) pin number array
+const uint32_t analogInputPin[] = {
+ 95, // 0
+ 96, // 1
+ 97, // 2
+ 98, // 3
+ 99, // 4
+ 100, // 5
+ 101, // 6
+ 102, // 7
+ 103, // 8
+ 12, // 9
+ 13, // 10
+ 24, // 11
+ 32, // 12
+ 33, // 13
+ 61, // 14
+ 62, // 15
+ 63, // 16
+ 69, // 17
+ 82, // 18
+ 83, // 19
+ 86, // 20
+ 90, // 21
+ 94 // 22
+};
+
+// ----------------------------------------------------------------------------
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief System Clock Configuration
+ * @param None
+ * @retval None
+ */
+WEAK void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
+
+
+ /** Supply configuration update enable
+ */
+ HAL_PWREx_ConfigSupply(PWR_EXTERNAL_SOURCE_SUPPLY);
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+
+ while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 1;
+ RCC_OscInitStruct.PLL.PLLN = 120;
+ RCC_OscInitStruct.PLL.PLLP = 2;
+ RCC_OscInitStruct.PLL.PLLQ = 5;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
+ RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
+ RCC_OscInitStruct.PLL.PLLFRACN = 0;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
+ | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+ RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+ Error_Handler();
+ }
+
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+}
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ARDUINO_NUCLEO_H745ZI_Q */
+
diff --git a/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/variant_NUCLEO_H745ZI_Q.h b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/variant_NUCLEO_H745ZI_Q.h
new file mode 100644
index 0000000000..b3ddc90d77
--- /dev/null
+++ b/variants/STM32H7xx/H745Z(G-I)T_H755ZIT/variant_NUCLEO_H745ZI_Q.h
@@ -0,0 +1,277 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2025, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#pragma once
+
+/*----------------------------------------------------------------------------
+ * STM32 pins number
+ *----------------------------------------------------------------------------*/
+//Arduino Uno compatible
+#define PB7 0
+#define PB6 1
+#define PG14 2
+#define PE13 3
+#define PE14 4
+#define PE11 5
+#define PA8 6
+#define PG12 7
+#define PG9 8
+#define PD15 9
+#define PD14 10
+#define PB5 11
+#define PA6 PIN_A9
+#define PA5 PIN_A10
+#define PB9 14
+#define PB8 15
+//CN7
+#define PC6 16
+#define PB15 17
+#define PB13 18
+#define PB12 19
+#define PA15 20
+#define PC7 21
+//#define PB5 22(11)
+#define PB3 23
+#define PA4 PIN_A11
+#define PB4 25
+//CN10
+#define PG6 26
+#define PB2 27
+#define PD13 28
+#define PD12 29
+#define PD11 30
+#define PE2 31
+#define PA0 PIN_A12
+#define PB0 PIN_A13
+#define PE0 34
+
+#define PB11 35
+#define PB10 36
+#define PE15 37
+#define PE6 38
+#define PE12 39
+#define PE10 40
+#define PE7 41
+#define PE8 42
+//CN8
+#define PC8 43
+#define PC9 44
+#define PC10 45
+#define PC11 46
+#define PC12 47
+#define PD2 48
+#define PG10 49
+#define PG8 50
+//CN9
+#define PD7 51
+#define PD6 52
+#define PD5 53
+#define PD4 54
+#define PD3 55
+//#define PE2 56(31)
+#define PE4 57
+#define PE5 58
+//#define PE6 59(38)
+#define PE3 60
+#define PF8 PIN_A14
+#define PF7 PIN_A15
+#define PF9 PIN_A16
+#define PD10 64
+
+#define PB14 65
+#define PD1 66
+#define PD0 67
+#define PF15 68
+#define PF14 PIN_A17
+//#define PB5 70(11)
+#define PE9 71
+//#define PB2 72(27)
+//CN11
+#define PA13 73
+#define PA14 74
+#define PC13 75
+#define PC14 76
+#define PC15 77
+#define PH0 78
+#define PH1 79
+#define PE1 80
+#define PD9 81
+#define PA1 PIN_A18
+#define PC1 PIN_A19
+#define PG13 84
+#define PG11 85
+//CN12
+#define PA7 PIN_A20
+#define PA9 87
+#define PA10 88
+#define PG7 89
+#define PC5 PIN_A21
+#define PD8 91
+#define PA12 92
+#define PA11 93
+#define PC4 PIN_A22
+
+#define PA3 PIN_A0
+#define PC0 PIN_A1
+#define PC3 PIN_A2
+#define PB1 PIN_A3
+#define PC2 PIN_A4
+#define PF11 PIN_A5
+
+#define PF6 PIN_A6
+#define PF10 PIN_A7
+#define PA2 PIN_A8
+
+// Alternate pins number
+#define PA0_ALT1 (PA0 | ALT1)
+#define PA1_ALT1 (PA1 | ALT1)
+#define PA1_ALT2 (PA1 | ALT2)
+#define PA2_ALT1 (PA2 | ALT1)
+#define PA2_ALT2 (PA2 | ALT2)
+#define PA3_ALT1 (PA3 | ALT1)
+#define PA3_ALT2 (PA3 | ALT2)
+#define PA4_ALT1 (PA4 | ALT1)
+#define PA4_ALT2 (PA4 | ALT2)
+#define PA5_ALT1 (PA5 | ALT1)
+#define PA6_ALT1 (PA6 | ALT1)
+#define PA7_ALT1 (PA7 | ALT1)
+#define PA7_ALT2 (PA7 | ALT2)
+#define PA7_ALT3 (PA7 | ALT3)
+#define PA9_ALT1 (PA9 | ALT1)
+#define PA10_ALT1 (PA10 | ALT1)
+#define PA11_ALT1 (PA11 | ALT1)
+#define PA12_ALT1 (PA12 | ALT1)
+#define PA15_ALT1 (PA15 | ALT1)
+#define PA15_ALT2 (PA15 | ALT2)
+#define PB0_ALT1 (PB0 | ALT1)
+#define PB0_ALT2 (PB0 | ALT2)
+#define PB1_ALT1 (PB1 | ALT1)
+#define PB1_ALT2 (PB1 | ALT2)
+#define PB3_ALT1 (PB3 | ALT1)
+#define PB3_ALT2 (PB3 | ALT2)
+#define PB4_ALT1 (PB4 | ALT1)
+#define PB4_ALT2 (PB4 | ALT2)
+#define PB5_ALT1 (PB5 | ALT1)
+#define PB5_ALT2 (PB5 | ALT2)
+#define PB6_ALT1 (PB6 | ALT1)
+#define PB6_ALT2 (PB6 | ALT2)
+#define PB7_ALT1 (PB7 | ALT1)
+#define PB8_ALT1 (PB8 | ALT1)
+#define PB9_ALT1 (PB9 | ALT1)
+#define PB14_ALT1 (PB14 | ALT1)
+#define PB14_ALT2 (PB14 | ALT2)
+#define PB15_ALT1 (PB15 | ALT1)
+#define PB15_ALT2 (PB15 | ALT2)
+#define PC0_ALT1 (PC0 | ALT1)
+#define PC0_ALT2 (PC0 | ALT2)
+#define PC1_ALT1 (PC1 | ALT1)
+#define PC1_ALT2 (PC1 | ALT2)
+#define PC4_ALT1 (PC4 | ALT1)
+#define PC5_ALT1 (PC5 | ALT1)
+#define PC6_ALT1 (PC6 | ALT1)
+#define PC7_ALT1 (PC7 | ALT1)
+#define PC8_ALT1 (PC8 | ALT1)
+#define PC9_ALT1 (PC9 | ALT1)
+#define PC10_ALT1 (PC10 | ALT1)
+#define PC11_ALT1 (PC11 | ALT1)
+#define PF8_ALT1 (PF8 | ALT1)
+#define PF9_ALT1 (PF9 | ALT1)
+
+
+
+#define NUM_DIGITAL_PINS 104
+#define NUM_DUALPAD_PINS 2
+#define NUM_ANALOG_INPUTS 23
+
+#define USE_PWR_DIRECT_SMPS_SUPPLY
+
+#define HSE_VALUE (8000000UL)
+
+// On-board LED pin number
+#ifndef LED_BUILTIN
+ #define LED_BUILTIN LED_GREEN
+#endif
+#define LED_GREEN PB0
+#define LED_YELLOW PE1
+#define LED_RED PB14
+
+// On-board user button
+#ifndef USER_BTN
+ #define USER_BTN PC13
+#endif
+
+// Timer Definitions
+// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin
+#ifndef TIMER_TONE
+ #define TIMER_TONE TIM6
+#endif
+#ifndef TIMER_SERVO
+ #define TIMER_SERVO TIM7
+#endif
+
+// UART Definitions
+#ifndef SERIAL_UART_INSTANCE
+ #define SERIAL_UART_INSTANCE 3
+#endif
+
+// Default pin used for generic 'Serial' instance
+// Mandatory for Firmata
+#ifndef PIN_SERIAL_RX
+ #define PIN_SERIAL_RX PD9
+#endif
+#ifndef PIN_SERIAL_TX
+ #define PIN_SERIAL_TX PD8
+#endif
+
+// Extra HAL modules
+#if !defined(HAL_DAC_MODULE_DISABLED)
+ #define HAL_DAC_MODULE_ENABLED
+#endif
+#if !defined(HAL_ETH_MODULE_DISABLED)
+ #define HAL_ETH_MODULE_ENABLED
+#endif
+#if !defined(HAL_QSPI_MODULE_DISABLED)
+ #define HAL_QSPI_MODULE_ENABLED
+#endif
+#if !defined(HAL_SD_MODULE_DISABLED)
+ #define HAL_SD_MODULE_ENABLED
+#endif
+
+/*----------------------------------------------------------------------------
+ * Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ // These serial port names are intended to allow libraries and architecture-neutral
+ // sketches to automatically default to the correct port name for a particular type
+ // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
+ // the first hardware serial port whose RX/TX pins are not dedicated to another use.
+ //
+ // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
+ //
+ // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
+ //
+ // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
+ //
+ // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
+ //
+ // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
+ // pins are NOT connected to anything by default.
+ #ifndef SERIAL_PORT_MONITOR
+ #define SERIAL_PORT_MONITOR Serial
+ #endif
+ #ifndef SERIAL_PORT_HARDWARE
+ #define SERIAL_PORT_HARDWARE Serial
+ #endif
+#endif
+
+