@@ -181,9 +181,9 @@ static inline uint32_t read_rs2(const hart_t *vm, uint32_t insn)
181181 return vm -> x_regs [decode_rs2 (insn )];
182182}
183183
184- static inline void ic_invalidate_all (hart_t * vm )
184+ static inline void icache_invalidate_all (hart_t * vm )
185185{
186- memset (& vm -> ic , 0 , sizeof (vm -> ic ));
186+ memset (& vm -> icache , 0 , sizeof (vm -> icache ));
187187}
188188
189189/* virtual addressing */
@@ -204,7 +204,7 @@ void mmu_invalidate(hart_t *vm)
204204 vm -> cache_store [set ].ways [way ].n_pages = 0xFFFFFFFF ;
205205 vm -> cache_store [set ].lru = 0 ; /* Reset LRU to way 0 */
206206 }
207- ic_invalidate_all (vm );
207+ icache_invalidate_all (vm );
208208}
209209
210210/* Invalidate MMU caches for a specific virtual address range.
@@ -370,29 +370,29 @@ static void mmu_fence(hart_t *vm, uint32_t insn UNUSED)
370370static void mmu_fetch (hart_t * vm , uint32_t addr , uint32_t * value )
371371{
372372 /* cache hit */
373- uint32_t idx = (addr >> IC_OFFSET_BITS ) & IC_INDEX_MASK ;
374- uint32_t tag = addr >> (IC_OFFSET_BITS + IC_INDEX_BITS );
375- icache_block_t * blk = & vm -> ic .i_block [idx ];
373+ uint32_t idx = (addr >> ICACHE_OFFSET_BITS ) & ICACHE_INDEX_MASK ;
374+ uint32_t tag = addr >> (ICACHE_OFFSET_BITS + ICACHE_INDEX_BITS );
375+ icache_block_t * blk = & vm -> icache .i_block [idx ];
376376
377377 if (likely (blk -> valid && blk -> tag == tag )) {
378378#ifdef MMU_CACHE_STATS
379379 vm -> cache_fetch .hits ++ ;
380380#endif
381- uint32_t ofs = addr & IC_BLOCK_MASK ;
381+ uint32_t ofs = addr & ICACHE_BLOCK_MASK ;
382382 * value = * (const uint32_t * ) (blk -> base + ofs );
383383 return ;
384384 }
385385
386386 /* search the victim cache */
387- for (int i = 0 ; i < VC_BLOCKS ; i ++ ) {
388- victim_cache_block_t * vblk = & vm -> ic .v_block [i ];
387+ for (int i = 0 ; i < VCACHE_BLOCKS ; i ++ ) {
388+ victim_cache_block_t * vblk = & vm -> icache .v_block [i ];
389389 if (vblk -> valid && vblk -> tag == tag ) {
390390 /* victim cache hit, block swap*/
391391 icache_block_t tmp = * blk ;
392392 * blk = * vblk ;
393393 * vblk = tmp ;
394394
395- uint32_t ofs = addr & IC_BLOCK_MASK ;
395+ uint32_t ofs = addr & ICACHE_BLOCK_MASK ;
396396 * value = * (const uint32_t * ) (blk -> base + ofs );
397397 return ;
398398 }
@@ -422,7 +422,7 @@ static void mmu_fetch(hart_t *vm, uint32_t addr, uint32_t *value)
422422 vm -> cache_fetch [index ].page_addr [(addr >> 2 ) & MASK (RV_PAGE_SHIFT - 2 )];
423423
424424 /* fill into the cache */
425- uint32_t block_off = (addr & RV_PAGE_MASK ) & ~IC_BLOCK_MASK ;
425+ uint32_t block_off = (addr & RV_PAGE_MASK ) & ~ICACHE_BLOCK_MASK ;
426426 blk -> base = (const uint8_t * ) vm -> cache_fetch [index ].page_addr + block_off ;
427427 blk -> tag = tag ;
428428 blk -> valid = true;
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