5-4 post before reddit

Author: thecodingchicken

_posts/2020-01-03-future-stuff-to-fix-or-add.md

@@ -0,0 +1,13 @@
+## Stuff to do in the future
+
+- The clock of the 74hc138's in the register module need to be hooked up to the inverted clock signal.
+- Hook up control lines for the ram in/ram out.  000 is disconnected, but 001-006 are connected up, where 001-006 are left-right.  
+
+
+
+
+
+---
+
+### Thoughts for the future
+- Use enamel wire to display contents of all registers?

_posts/2025-05-03-register-build.md

@@ -13,6 +13,15 @@ I'll probably wire it all up as if the NOR's in place, but just can't test it un
 So I think the final layout of the board will be 3 breadboards, with the bottom one handling the control logic(3-8 decoding for both inputs and outputs), NOR gates for combining clock and register in controls, and maybe some led stuff.  Or, more likely, space for something else that I'm forgetting.  I do need to implement a shift register somewhere I suppose...don't know how that's gonna happen.
 But that's a topic for another day, I need to get some sleep.  
 
+
 ---
 ### Things to consider for the future
-How do I want to implement a shift register?  Jameco doesn't have a 74hc194 4-bit shift register, need to look around for other options.  
+How do I want to implement a shift register?  Jameco doesn't have a 74hc194 4-bit shift register, need to look around for other options.  
+
+---
+## Here's my progress for the day.
+<figure>
+  <div>
+  <img src="{{site.url}}/assets/img/20250504_092106.jpeg" alt="Day 1 register progress"/>
+  </div>
+</figure>

_posts/2025-05-04-register-control-logic.md

@@ -1,4 +1,23 @@
 ## Continuing the register build
 
 I've setup the decoding logic for the registers, which will consist of two groups, ram in, and ram out.  The ram in is controlled by a [74hc138](https://www.mouser.com/datasheet/2/149/mm74hc138-303670.pdf) and two [74hc02](https://www.jameco.com/Jameco/Products/ProdDS/45188FSC.pdf).  The NOR gate is required to combine the control logic and the clock signal, otherwise there's no way to make it only work on the clock pulse.  Ram out is controlled by another 74HC138 and two [74hc04](https://www.jameco.com/Jameco/Products/ProdDS/45209FSC.pdf)'s, as the output on the 245's are active LOW.  
-I've decided on using yellow for control signals, and I guess gray for modified control signals.  Plus, more colors is more better, right?  I've started a 
+I've decided on using yellow for control signals, and I guess gray for modified control signals.  Plus, more colors is more better, right?  I've started a document where I organize all of that [here](https://thecodingchicken.github.io/2020/01/01/color_design.html).  I also have the one with stuff to print out [here](https://thecodingchicken.github.io/2020/01/02/stuff-to-print.html)
+
+---
+
+### A realization
+So, the chips require active LOW, and funnily enough the 74hc138 provides an active low, so this 6-chip solution that wouldn't work turned into two chips.  I can put the clock on pin 6 of the 138's, which is the positive enable of them.  And this'll be the NEGATIVE clock signal.  I'm going to leave Y0(pin 15) unconnected, so in the default configuration, no register will be selected.  
+
+
+---
+## Here's my progress so far
+<figure>
+  <div>
+  <img src="{{site.url}}/assets/img/20250504_103945.jpeg" alt="Day 1 register progress"/>
+  </div>
+</figure>
+
+### Bill of Materials
+- 74hc245 Octal 3-state transceiver (6)
+- 74hc574 3-state Octal D-Type Edge-Triggered Flip-Flop (6)
+- 74h138 3-line to 8-line decoder (2)