5-27

Author: thecodingchicken

_posts/2020-01-05-current-jameco-ordering-list.md

@@ -1,5 +1,21 @@
 ## Stuff I need to buy
 
 - Potentially another 100ft purple wire roll (2154880)
+- Potentially another 100ft grey wire roll(2154898)
 - 20x 74h595 shift registers (serial-in parallel-out) I use these everywhere it seems
-- 10x 1N5817 schottky diodes - for arduino nano, use to not allow backfeed(also lower forward voltage drop)
+- 10x 74hc165 shift registers (parallel-in serial-out)
+- 10x 1N5817 schottky diodes - for arduino nano, use to not allow backfeed(also lower forward voltage drop)
+- 10x 74hc191 synchronous binary up/down counter - 4 are being used for the stack pointer
+	Stack pointer uses 4 counters, high and low byte SP-H, SP-L
+	Control signals:
+		High byte in, high byte out
+		low byte in, low byte out
+		Stack pointer count enable
+		Stack pointer up/down signal
+		6 signals total
+		can use a 3-8 decoder
+		(BLANK, high in, high out, low in, low out), stack count enable, stack pointer up/down
+- 30x BC327 PNP transistors - for multiplexing outputs
+- 5x atmega328p
+- 10x crystal 16.000MHz
+<!-- - aries 40-6554-10 zif socket -->

_posts/2025-05-25-progress.md

@@ -0,0 +1,180 @@
+## MAR Progress, day 2
+
+Goooooood morning!  Who woke up early on a Sunday, so they decided to spend their morning starting off with wiring for a chip that doesn't exist here yet.  Ha, wouldn't be me, right?
+
+---
+The amount of time that I've spent trying to figure out this control logic, realizing flaws that I've made today is stupid.  I think I've spent at least an hour or two trying to do it in the fewest amount of chips, and on the rising edge...yeah.  
+
+
+<!-- 
+Revised Connection List
+Below is the updated connection list, incorporating the 74HC138 output shift and correcting the Second 74HC08 Gate 2 output destinations to include Second 74HC08 Gate 1 input A.
+Breadboard 2: 74HC138 (Control Signal Decoder)
+Pin Connections:
+A (pin 1): Control unit A line.
+
+B (pin 2): Control unit B line.
+
+C (pin 3): Control unit C line.
+
+G1 (pin 6): Control unit MEM_EN (active high).
+
+G2A (pin 4): GND.
+
+G2B (pin 5): GND.
+
+Y0 (pin 15): Unconnected.
+
+Y1 (pin 14): To 74HC04 Gate 1 input (Breadboard 1, MAR_LOAD_L).
+
+Y2 (pin 13): To 74HC04 Gate 2 input (Breadboard 1, MAR_LOAD_H).
+
+Y3 (pin 12): To 74HC04 Gate 3 input (Breadboard 1, READ).
+
+Y4 (pin 11): To 74HC04 Gate 4 input (Breadboard 1, WRITE).
+
+Y5–Y7 (pins 10, 9, 7): Unconnected.
+
+VCC (pin 16): 5V.
+
+GND (pin 8): GND.
+
+Breadboard 1: 74HC04 (Hex Inverter)
+Pin Connections:
+Gate 1 (1A, pin 1; 1Y, pin 2): 1A = 74HC138 Y1 (MAR_LOAD_L), 1Y = NOT Y1 to Second 74HC08 Gate 3 input A.
+
+Gate 2 (2A, pin 3; 2Y, pin 4): 2A = 74HC138 Y2 (MAR_LOAD_H), 2Y = NOT Y2 to Second 74HC08 Gate 4 input A.
+
+Gate 3 (3A, pin 5; 3Y, pin 6): 3A = 74HC138 Y3 (READ), 3Y = NOT READ to First 74HC08 Gate 1 input A.
+
+Gate 4 (4A, pin 9; 4Y, pin 8): 4A = 74HC138 Y4 (WRITE), 4Y = NOT WRITE to First 74HC08 Gate 2 input A.
+
+Gate 5 (5A, pin 11; 5Y, pin 10): 5A = 74HC139 1Y0 (ROM_CE), 5Y = NOT ROM_CE to SST39SF010 CE and OE.
+
+Gate 6 (6A, pin 13; 6Y, pin 12): 6A = A15 (MAR-H Q7), 6Y = NOT A15 to 74HC139 2E.
+
+VCC (pin 14): 5V.
+
+GND (pin 7): GND.
+
+Breadboard 1: First 74HC08 (AND Gates)
+Pin Connections:
+Gate 1 (1A, pin 1; 1B, pin 2; 1Y, pin 3): 1A = 74HC04 3Y (NOT READ), 1B = Clock, 1Y = Final READ to First 74HC08 Gate 3 input B.
+
+Gate 2 (2A, pin 4; 2B, pin 5; 2Y, pin 6): 2A = 74HC04 4Y (NOT WRITE), 2B = Clock, 2Y = Final WRITE to Second 74HC08 Gate 1 input B.
+
+Gate 3 (3A, pin 9; 3B, pin 10; 3Y, pin 8): 3A = Second 74HC08 2Y (Final RAM_CE), 3B = First 74HC08 1Y (Final READ), 3Y = 62256 OE.
+
+Gate 4 (4A, pin 12; 4B, pin 13; 4Y, pin 11): 4A = A15 (MAR-H Q7), 4B = A14 (MAR-H Q6), 4Y = A15 ∧ A14 to 74HC139 1E.
+
+VCC (pin 14): 5V.
+
+GND (pin 7): GND.
+
+Breadboard 1: Second 74HC08 (AND Gates)
+Pin Connections:
+Gate 1 (1A, pin 1; 1B, pin 2; 1Y, pin 3): 1A = Second 74HC08 2Y (Final RAM_CE), 1B = First 74HC08 2Y (Final WRITE), 1Y = 62256 WE.
+
+Gate 2 (2A, pin 4; 2B, pin 5; 2Y, pin 6): 2A = 74HC139 2Y0 (RAM_CE), 2B = MEM_EN (control unit), 2Y = Final RAM_CE to 62256 CE, First 74HC08 Gate 3 input A, Second 74HC08 Gate 1 input A.
+
+Gate 3 (3A, pin 9; 3B, pin 10; 3Y, pin 8): 3A = 74HC04 1Y (NOT Y1), 3B = Clock, 3Y = Final MAR_LOAD_L to MAR-L CP.
+
+Gate 4 (4A, pin 12; 4B, pin 13; 4Y, pin 11): 4A = 74HC04 2Y (NOT Y2), 4B = Clock, 4Y = Final MAR_LOAD_H to MAR-H CP.
+
+VCC (pin 14): 5V.
+
+GND (pin 7): GND.
+
+Breadboard 1: 74HC139 (Dual 2-to-4 Decoder)
+Pin Connections:
+1E (pin 1): First 74HC08 4Y (A15 ∧ A14).
+
+1A (pin 2): A12 (MAR-H Q4).
+
+1B (pin 3): A13 (MAR-H Q5).
+
+1Y0 (pin 4): ROM_CE to 74HC04 5A.
+
+1Y1–1Y3 (pins 5–7): Unconnected.
+
+2E (pin 15): 74HC04 6Y (NOT A15).
+
+2A (pin 14): A14 (MAR-H Q6).
+
+2B (pin 13): GND.
+
+2Y0 (pin 12): RAM_CE to Second 74HC08 2A.
+
+2Y1–2Y3 (pins 11–9): Unconnected.
+
+VCC (pin 16): 5V.
+
+GND (pin 8): GND.
+
+Breadboard 1: 74HC377 (MAR-L, A0–A7)
+Pin Connections:
+D0–D7 (pins 3, 6, 8, 13, 14, 17, 18, 4): Data bus (D0–D7).
+
+Q0–Q7 (pins 2, 5, 9, 12, 15, 16, 19, 7): A0–A7 to ROM A0–A7, RAM A0–A7.
+
+CP (pin 11): Second 74HC08 3Y (Final MAR_LOAD_L).
+
+E (pin 1): GND.
+
+VCC (pin 20): 5V.
+
+GND (pin 10): GND.
+
+Breadboard 1: 74HC377 (MAR-H, A8–A15)
+Pin Connections:
+D0–D7 (pins 3, 6, 8, 13, 14, 17, 18, 4): Data bus (D0–D7).
+
+Q0–Q7 (pins 2, 5, 9, 12, 15, 16, 19, 7): A8–A15 to ROM A8–A15, RAM A8–A14, A15 to 74HC04 6A and First 74HC08 4A, A14 to First 74HC08 4B and 74HC139 2A, A13 to 74HC139 1B, A12 to 74HC139 1A.
+
+CP (pin 11): Second 74HC08 4Y (Final MAR_LOAD_H).
+
+E (pin 1): GND.
+
+VCC (pin 20): 5V.
+
+GND (pin 10): GND.
+
+Breadboard 1: SST39SF010 (ROM)
+Pin Connections:
+A0–A15 (pins 10–18, 7–5, 27, 26, 23, 25): MAR-L Q0–Q7 (A0–A7), MAR-H Q0–Q7 (A8–A15).
+
+DQ0–DQ7 (pins 11, 13, 15, 17, 19, 8, 6, 4): Data bus (D0–D7).
+
+CE (pin 3): 74HC04 5Y (NOT ROM_CE).
+
+OE (pin 1): 74HC04 5Y (NOT ROM_CE).
+
+WE (pin 2): 5V.
+
+VCC (pins 28, 20): 5V.
+
+GND (pins 14, 22): GND.
+
+Breadboard 1: 62256 (RAM)
+Pin Connections:
+A0–A14 (pins 10–18, 7–5, 27, 26): MAR-L Q0–Q7 (A0–A7), MAR-H Q0–Q6 (A8–A14).
+
+DQ0–DQ7 (pins 11, 13, 15, 17, 19, 8, 6, 4): Data bus (D0–D7).
+
+CE (pin 20): Second 74HC08 2Y (Final RAM_CE).
+
+OE (pin 22): First 74HC08 3Y (Final RAM_CE ∧ Final READ).
+
+WE (pin 21): Second 74HC08 1Y (Final RAM_CE ∧ Final WRITE).
+
+VCC (pin 28): 5V.
+
+GND (pin 14): GND.
+
+ -->
+
+
+I've commented out the connection listing from grok.  That's probably going to get me, but thankfully most of that logic is on top of the data/address wires, so it won't be like undoing the whole thing.  Testing&debugging it will still be fun, but it will mostly involve reading&writing at several key addresses.  
+
+---
+

_posts/2025-05-27-rained-out.md

@@ -0,0 +1,9 @@
+## Rained out
+
+Went out to work this morning, knowing that it was going to rain a little bit....yeah no.  We're back at the hotel, so I guess I get to work on the project more.  I also don't have internet at the hotel, because the wifi's down.  Ha!  But I have a couple datasheets loaded right now and I can download more if I have to.  
+
+---
+
+
+I don't even remember what else I did this day lol.  And I'm writing this the 28th
+But I did go back to work