x86: fix ruff issues on gen_mmu.py

Fixes issues found by ruff on gen_mmu.py.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>

Author: dcpleung

.ruff-excludes.toml

@@ -5,12 +5,6 @@
 # remove entries for files that pass CI compliance testing.
 
 [lint.per-file-ignores]
-"./arch/x86/gen_mmu.py" = [
-    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
-    "UP031",    # https://docs.astral.sh/ruff/rules/printf-string-formatting
-    "UP034",    # https://docs.astral.sh/ruff/rules/extraneous-parentheses
-    "UP039",    # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses
-]
 "./arch/x86/zefi/zefi.py" = [
     "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
     "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports

arch/x86/gen_mmu.py

@@ -65,20 +65,19 @@
 top-level paging structure as it is written out last.
 """
 
-import sys
-import array
 import argparse
+import array
 import ctypes
 import os
-import struct
 import re
+import struct
+import sys
 import textwrap
 
-from packaging import version
-
 import elftools
 from elftools.elf.elffile import ELFFile
 from elftools.elf.sections import SymbolTableSection
+from packaging import version
 
 if version.parse(elftools.__version__) < version.parse('0.24'):
     sys.exit("pyelftools is out of date, need version 0.24 or later")
@@ -134,9 +133,9 @@ def error(text):
 def align_check(base, size, scope=4096):
     """Make sure base and size are page-aligned"""
     if (base % scope) != 0:
-        error("unaligned base address %x" % base)
+        error(f"unaligned base address {base:x}")
     if (size % scope) != 0:
-        error("Unaligned region size 0x%x for base %x" % (size, base))
+        error(f"Unaligned region size 0x{size:x} for base {base:x}")
 
 
 def dump_flags(flags):
@@ -184,7 +183,7 @@ def round_down(val, align):
 # access or set caching properties at leaf levels.
 INT_FLAGS = FLAG_P | FLAG_RW | FLAG_US
 
-class MMUTable():
+class MMUTable:
     """Represents a particular table in a set of page tables, at any level"""
 
     def __init__(self):
@@ -261,9 +260,9 @@ def map(self, virt_addr, phys_addr, entry_flags):
         this is the physical address of the next level table"""
         index = self.entry_index(virt_addr)
 
-        verbose("%s: mapping 0x%x to 0x%x : %s" %
-                (self.__class__.__name__,
-                 phys_addr, virt_addr, dump_flags(entry_flags)))
+        verbose(f"{self.__class__.__name__:s}: "
+                f"mapping 0x{phys_addr:x} to 0x{virt_addr:x} : "
+                f"{dump_flags(entry_flags):s}")
 
         self.entries[index] = ((phys_addr & self.addr_mask) |
                                (entry_flags & self.supported_flags))
@@ -274,9 +273,9 @@ def set_perms(self, virt_addr, entry_flags):
         Unsupported flags will be filtered out."""
         index = self.entry_index(virt_addr)
 
-        verbose("%s: changing perm at 0x%x : %s" %
-                (self.__class__.__name__,
-                 virt_addr, dump_flags(entry_flags)))
+        verbose(f"{self.__class__.__name__:s}: "
+                f"changing perm at 0x{virt_addr:x} : "
+                f"{dump_flags(entry_flags):s}")
 
         self.entries[index] = ((self.entries[index] & self.addr_mask) |
                                (entry_flags & self.supported_flags))
@@ -336,7 +335,7 @@ class PtXd(Pt):
                        FLAG_D | FLAG_IGNORED0 | FLAG_IGNORED1 | FLAG_IGNORED2)
 
 
-class PtableSet():
+class PtableSet:
     """Represents a complete set of page tables for any paging mode"""
 
     def __init__(self, pages_start):
@@ -345,8 +344,8 @@ def __init__(self, pages_start):
         self.toplevel = self.levels[0]()
         self.page_pos = pages_start
 
-        debug("%s starting at physical address 0x%x" %
-              (self.__class__.__name__, self.page_pos))
+        debug(f"{self.__class__.__name__:s} "
+              f"starting at physical address 0x{self.page_pos:x}")
 
         # Database of page table pages. Maps physical memory address to
         # MMUTable objects, excluding the top-level table which is tracked
@@ -408,8 +407,7 @@ def new_child_table(self, table, virt_addr, depth):
         """Create a new child table"""
         new_table_addr = self.get_new_mmutable_addr()
         new_table = self.levels[depth]()
-        debug("new %s at physical addr 0x%x"
-                      % (self.levels[depth].__name__, new_table_addr))
+        debug(f"new {self.levels[depth].__name__:s} at physical addr 0x{new_table_addr:x}")
         self.tables[new_table_addr] = new_table
         table.map(virt_addr, new_table_addr, INT_FLAGS)
 
@@ -436,17 +434,16 @@ def map_page(self, virt_addr, phys_addr, flags, reserve, level=PT_LEVEL):
 
     def reserve(self, virt_base, size, to_level=PT_LEVEL):
         """Reserve page table space with already aligned virt_base and size"""
-        debug("Reserving paging structures for 0x%x (0x%x)" %
-              (virt_base, size))
+        debug(f"Reserving paging structures for 0x{virt_base:x} (0x{size:x})")
 
         align_check(virt_base, size)
 
         # How much memory is covered by leaf page table
         scope = 1 << self.levels[PD_LEVEL].addr_shift
 
         if virt_base % scope != 0:
-            error("misaligned virtual address space, 0x%x not a multiple of 0x%x" %
-                  (virt_base, scope))
+            error(f"misaligned virtual address space, 0x{virt_base:x} "
+                  f"not a multiple of 0x{scope:x}")
 
         for addr in range(virt_base, virt_base + size, scope):
             self.map_page(addr, 0, 0, True, to_level)
@@ -473,8 +470,7 @@ def map(self, phys_base, virt_base, size, flags, level=PT_LEVEL):
 
         scope = 1 << self.levels[level].addr_shift
 
-        debug("Mapping 0x%x (0x%x) to 0x%x: %s" %
-                (phys_base, size, virt_base, dump_flags(flags)))
+        debug(f"Mapping 0x{phys_base:x} (0x{size:x}) to 0x{virt_base:x}: {dump_flags(flags):s}")
 
         align_check(phys_base, size, scope)
         align_check(virt_base, size, scope)
@@ -537,8 +533,7 @@ def set_region_perms(self, name, flags, level=PT_LEVEL):
         if size == 0:
             return
 
-        debug("change flags for %s at 0x%x (0x%x): %s" %
-              (name, base, size, dump_flags(flags)))
+        debug(f"change flags for {name:s} at 0x{base:x} (0x{size:x}): {dump_flags(flags):s}")
 
         num_levels = len(self.levels) + level + 1
         scope = 1 << self.levels[level].addr_shift
@@ -556,8 +551,7 @@ def set_region_perms(self, name, flags, level=PT_LEVEL):
                     table = self.tables[table.lookup(addr)]
                 table.set_perms(addr, flags)
         except KeyError:
-            error("no mapping for %s region 0x%x (size 0x%x)" %
-                  (name, base, size))
+            error(f"no mapping for {name:s} region 0x{base:x} (size 0x{size:x})")
 
     def write_output(self, filename):
         """Write the page tables to the output file in binary format"""
@@ -574,9 +568,8 @@ def write_output(self, filename):
             # in PAE, the top-level PDPT has only 4 entries and is not a
             # full page in size. We do not put it in the tables dictionary
             # and treat it as a special case.
-            debug("top-level %s at physical addr 0x%x" %
-                  (self.toplevel.__class__.__name__,
-                   self.get_new_mmutable_addr()))
+            debug(f"top-level {self.toplevel.__class__.__name__:s} at "
+                  f"physical addr 0x{self.get_new_mmutable_addr():x}")
             top_level_bin = self.toplevel.get_binary()
             output_fp.write(top_level_bin)
             written_size += len(top_level_bin)
@@ -666,7 +659,7 @@ def map_extra_regions(pt):
         elements = entry.split(',')
 
         if len(elements) < 2:
-            error("Not enough arguments for --map %s" % entry)
+            error(f"Not enough arguments for --map {entry:s}")
 
         one_map = {}
 
@@ -681,7 +674,7 @@ def map_extra_regions(pt):
 
             # Check for allowed flags
             if not bool(re.match('^[LUWXD]*$', map_flags)):
-                error("Unrecognized flags: %s" % map_flags)
+                error(f"Unrecognized flags: {map_flags:s}")
 
             flags = FLAG_P | ENTRY_XD
             if 'W' in map_flags:
@@ -716,8 +709,8 @@ def map_extra_regions(pt):
         # Check if addresses have already been mapped.
         # Error out if so as they could override kernel mappings.
         if pt.is_region_mapped(virt, size, level):
-            error(("Region 0x%x (%d) already been mapped "
-                   "for --map %s" % (virt, size, one_map['cmdline'])))
+            error(f"Region 0x{virt:x} ({size:d}) already been mapped "
+                  f"for --map {one_map['cmdline']:x}")
 
         # Reserve space in page table, and map the region
         pt.reserve_unaligned(virt, size, level)
@@ -746,7 +739,7 @@ def main():
     else:
         pclass = Ptables32bit
 
-    debug("building %s" % pclass.__name__)
+    debug(f"building {pclass.__name__:s}")
 
     vm_base = syms["CONFIG_KERNEL_VM_BASE"]
     vm_size = syms["CONFIG_KERNEL_VM_SIZE"]
@@ -778,23 +771,22 @@ def main():
 
     ptables_phys = syms["z_x86_pagetables_start"] + virt_to_phys_offset
 
-    debug("Address space: 0x%x - 0x%x size 0x%x" %
-          (vm_base, vm_base + vm_size - 1, vm_size))
+    debug(f"Address space: 0x{vm_base:x} - 0x{vm_base + vm_size - 1:x} size 0x{vm_size:x}")
 
-    debug("Zephyr image: 0x%x - 0x%x size 0x%x" %
-          (image_base, image_base + image_size - 1, image_size))
+    debug(f"Zephyr image: 0x{image_base:x} - 0x{image_base + image_size - 1:x} "
+          f"size 0x{image_size:x}")
 
     if virt_to_phys_offset != 0:
-        debug("Physical address space: 0x%x - 0x%x size 0x%x" %
-              (sram_base, sram_base + sram_size - 1, sram_size))
+        debug(f"Physical address space: 0x{sram_base:x} - 0x{sram_base + sram_size - 1:x} "
+              f"size 0x{sram_size:x}")
 
     is_perm_regions = isdef("CONFIG_SRAM_REGION_PERMISSIONS")
 
     # Are pages in non-boot, non-pinned sections present at boot.
     is_generic_section_present = isdef("CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT")
 
     if image_size >= vm_size:
-        error("VM size is too small (have 0x%x need more than 0x%x)" % (vm_size, image_size))
+        error(f"VM size is too small (have 0x{vm_size:x} need more than 0x{image_size:x})")
 
     map_flags = 0
 
@@ -835,8 +827,7 @@ def main():
         # from real mode
         locore_base = syms["_locore_start"]
         locore_size = syms["_lodata_end"] - locore_base
-        debug("Base addresses: physical 0x%x size 0x%x" % (locore_base,
-                                                         locore_size))
+        debug(f"Base addresses: physical 0x{locore_base:x} size 0x{locore_size:x}")
         pt.map(locore_base, None, locore_size, map_flags | FLAG_P | ENTRY_RW)
 
     if isdef("CONFIG_XIP"):
@@ -917,7 +908,7 @@ def main():
             pt.set_region_perms("__x86shadowstack", FLAG_P | FLAG_D | ENTRY_XD)
 
     written_size = pt.write_output(args.output)
-    debug("Written %d bytes to %s" % (written_size, args.output))
+    debug(f"Written {written_size:d} bytes to {args.output:s}")
 
     # Warn if reserved page table is not of correct size
     if reserved_pt_size and written_size != reserved_pt_size:
@@ -935,9 +926,8 @@ def main():
 
         reason = "big" if reserved_pt_size > written_size else "small"
 
-        error(("Reserved space for page table is too %s."
-               " Set CONFIG_X86_EXTRA_PAGE_TABLE_PAGES=%d") %
-               (reason, extra_pages_needed))
+        error(f"Reserved space for page table is too {reason:s}."
+              f" Set CONFIG_X86_EXTRA_PAGE_TABLE_PAGES={extra_pages_needed:d}")
 
 
 if __name__ == "__main__":