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Update to QPDS 25.3 tools release
This is a significant update to all hardware and software objects within this repo as they are all updated to build under the QPDS 25.3 tools environment. Some of the more notable changes are listed below: The following IP cores are updated in the 25.3 tools: intel_agilex_5_soc instance 11.1.0 emif_io96b_hps 4.1.0 altera_msgdma 19.3.2 altera_avalon_sysid_qsys 20.0.0 altera_axi_bridge 19.10.0 The 25.3 tools do not generate the same rtl source that we hacked with a sed script in the F2H bridge example in previous releases so we've modified the custom terminator component and the AXI4 interconnect adapter component to add the required smmu id signals so we can drive the appropriate values directly into the F2H bridge. The HPS component configuration is modified to enable the smmu interface on the F2H bridge. An HPS IO hash mismatch arose in the F2H bridge example that appears to be cured by adding an altera_axi_bridge between the LWH2F bridge and the subordinates that connect to it. At this time we're going to go with this modification to keep the HPS IO hashes consistent across all of the example designs. We may need to do something more agressive in the future. u-boot-socfpga, arm-trusted-firmware and linux-socfpga are updated to the latest tag, QPDS25.3_REL_GSRD_PR toybox is updated to the latest tag, 0.8.13 Signed-off-by: Rod Frazer <rod.frazer@altera.com>
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‎README.md‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
- **title**: agilex5-demo-hps2fpga-interfaces
88
- **source**: GitHub
99
- **family**: Agilex 5
10-
- **quartus_version**: Version 25.1.1 Build 125 07/31/2025 SC Pro Edition
10+
- **quartus_version**: Version 25.3.0 Build 109 09/24/2025 SC Pro Edition
1111
- **devkit**: Agilex 5 FPGA E-Series 065B Premium Development Kit, and others
1212
- **device_part**: A5ED065BB32AE5SR0, A5ED065BB32AE4SR0, A5ED065BB32AE6SR0, A5ED013BM16AE4SCS
1313
- **description**: Agilex 5 HPS-to-FPGA interfaces demos.

‎brd_altera_a5e013cs/hw_base/a55_do_create_no_pins_hps.tcl‎

Lines changed: 14 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,20 +1,21 @@
11
#
2+
# SPDX-FileCopyrightText: Copyright (C) 2024 Intel Corporation
23
# SPDX-FileCopyrightText: Copyright (C) 2025 Altera Corporation
34
# SPDX-License-Identifier: MIT-0
45
#
56
proc do_create_no_pins_hps {} {
67
# create the system
78
create_system no_pins_hps
89
set_project_property BOARD {default}
9-
#set_project_property DEVICE {A5ED013BB32AE5S}
10+
#set_project_property DEVICE {A5ED013BM16AE4SCS}
1011
#set_project_property DEVICE_FAMILY {Agilex 5}
1112
set_project_property HIDE_FROM_IP_CATALOG {false}
1213
set_use_testbench_naming_pattern 0 {}
1314

1415
# add HDL parameters
1516

1617
# add the components
17-
add_component agilex_5_soc ip/no_pins_hps/agilex_5_soc.ip intel_agilex_5_soc agilex_5_soc 9.0.0
18+
add_component agilex_5_soc ip/no_pins_hps/agilex_5_soc.ip intel_agilex_5_soc agilex_5_soc 11.1.0
1819
load_component agilex_5_soc
1920
set_component_parameter_value ATB_Enable {0}
2021
set_component_parameter_value CM_Mode {N/A}
@@ -24,6 +25,7 @@ proc do_create_no_pins_hps {} {
2425
set_component_parameter_value Debug_APB_Enable {0}
2526
set_component_parameter_value ED_en_questa {1}
2627
set_component_parameter_value ED_en_riviera {0}
28+
set_component_parameter_value ED_en_sim_gen {1}
2729
set_component_parameter_value ED_en_synth_gen {0}
2830
set_component_parameter_value ED_en_vcsmx {1}
2931
set_component_parameter_value ED_en_xcelium {1}
@@ -317,7 +319,7 @@ proc do_create_no_pins_hps {} {
317319
set_component_parameter_value User1_clk_freq {200.0}
318320
set_component_parameter_value User1_clk_src_select {1}
319321
set_component_parameter_value eosc1_clk_mhz {25.0}
320-
set_component_parameter_value f2s_SMMU {0}
322+
set_component_parameter_value f2s_SMMU {1}
321323
set_component_parameter_value f2s_address_width {32}
322324
set_component_parameter_value f2s_data_width {256}
323325
set_component_parameter_value f2s_mode {ace5lite}
@@ -414,6 +416,7 @@ proc do_create_no_pins_hps {} {
414416
set_instantiation_interface_parameter_value hps2fpga maximumOutstandingTransactions {1}
415417
set_instantiation_interface_parameter_value hps2fpga maximumOutstandingWrites {1}
416418
set_instantiation_interface_parameter_value hps2fpga noRepeatedIdsBetweenSubordinates {0}
419+
set_instantiation_interface_parameter_value hps2fpga optionalAssociatedReset {false}
417420
set_instantiation_interface_parameter_value hps2fpga poison {false}
418421
set_instantiation_interface_parameter_value hps2fpga readIssuingCapability {16}
419422
set_instantiation_interface_parameter_value hps2fpga securityAttribute {false}
@@ -482,6 +485,7 @@ proc do_create_no_pins_hps {} {
482485
set_instantiation_interface_parameter_value lwhps2fpga maximumOutstandingTransactions {1}
483486
set_instantiation_interface_parameter_value lwhps2fpga maximumOutstandingWrites {1}
484487
set_instantiation_interface_parameter_value lwhps2fpga noRepeatedIdsBetweenSubordinates {0}
488+
set_instantiation_interface_parameter_value lwhps2fpga optionalAssociatedReset {false}
485489
set_instantiation_interface_parameter_value lwhps2fpga poison {false}
486490
set_instantiation_interface_parameter_value lwhps2fpga readIssuingCapability {16}
487491
set_instantiation_interface_parameter_value lwhps2fpga securityAttribute {false}
@@ -692,6 +696,7 @@ proc do_create_no_pins_hps {} {
692696
set_instantiation_interface_parameter_value f2sdram maximumOutstandingReads {1}
693697
set_instantiation_interface_parameter_value f2sdram maximumOutstandingTransactions {1}
694698
set_instantiation_interface_parameter_value f2sdram maximumOutstandingWrites {1}
699+
set_instantiation_interface_parameter_value f2sdram optionalAssociatedReset {false}
695700
set_instantiation_interface_parameter_value f2sdram poison {false}
696701
set_instantiation_interface_parameter_value f2sdram readAcceptanceCapability {16}
697702
set_instantiation_interface_parameter_value f2sdram readDataReorderingDepth {1}
@@ -778,6 +783,7 @@ proc do_create_no_pins_hps {} {
778783
set_instantiation_interface_parameter_value fpga2hps dfhParameterId {}
779784
set_instantiation_interface_parameter_value fpga2hps dfhParameterName {}
780785
set_instantiation_interface_parameter_value fpga2hps dfhParameterVersion {}
786+
set_instantiation_interface_parameter_value fpga2hps isTranslator {false}
781787
set_instantiation_interface_parameter_value fpga2hps poison {false}
782788
set_instantiation_interface_parameter_value fpga2hps readAcceptanceCapability {16}
783789
set_instantiation_interface_parameter_value fpga2hps readDataReorderingDepth {1}
@@ -833,7 +839,11 @@ proc do_create_no_pins_hps {} {
833839
add_instantiation_interface_port fpga2hps fpga2hps_rvalid rvalid 1 STD_LOGIC Output
834840
add_instantiation_interface_port fpga2hps fpga2hps_rready rready 1 STD_LOGIC Input
835841
add_instantiation_interface_port fpga2hps fpga2hps_aruser aruser 8 STD_LOGIC_VECTOR Input
842+
add_instantiation_interface_port fpga2hps fpga2hps_armmusecsid armmusecsid 1 STD_LOGIC Input
843+
add_instantiation_interface_port fpga2hps fpga2hps_armmusid armmusid 16 STD_LOGIC_VECTOR Input
836844
add_instantiation_interface_port fpga2hps fpga2hps_awuser awuser 8 STD_LOGIC_VECTOR Input
845+
add_instantiation_interface_port fpga2hps fpga2hps_awmmusecsid awmmusecsid 1 STD_LOGIC Input
846+
add_instantiation_interface_port fpga2hps fpga2hps_awmmusid awmmusid 16 STD_LOGIC_VECTOR Input
837847
add_instantiation_interface_port fpga2hps fpga2hps_arregion arregion 4 STD_LOGIC_VECTOR Input
838848
add_instantiation_interface_port fpga2hps fpga2hps_awregion awregion 4 STD_LOGIC_VECTOR Input
839849
add_instantiation_interface_port fpga2hps fpga2hps_wuser wuser 8 STD_LOGIC_VECTOR Input
@@ -906,7 +916,7 @@ proc do_create_no_pins_hps {} {
906916
add_instantiation_interface_port io96b0_to_hps io96b0_to_hps_axi4_ch0_arprot axi4_ch0_arprot 3 STD_LOGIC_VECTOR Output
907917
add_instantiation_interface_port io96b0_to_hps io96b0_to_hps_axi4_ch0_awprot axi4_ch0_awprot 3 STD_LOGIC_VECTOR Output
908918
save_instantiation
909-
add_component emif_bank3a_hps ip/no_pins_hps/emif_bank3a_hps.ip emif_io96b_hps emif_bank3a_hps 4.0.0
919+
add_component emif_bank3a_hps ip/no_pins_hps/emif_bank3a_hps.ip emif_io96b_hps emif_bank3a_hps 4.1.0
910920
load_component emif_bank3a_hps
911921
set_component_parameter_value EMIF_PROTOCOL {LPDDR4}
912922
set_component_parameter_value EMIF_REF_CLK_SHARING {0}

‎brd_altera_a5e013cs/hw_base/a76_do_create_no_pins_hps.tcl‎

Lines changed: 14 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,20 +1,21 @@
11
#
2+
# SPDX-FileCopyrightText: Copyright (C) 2024 Intel Corporation
23
# SPDX-FileCopyrightText: Copyright (C) 2025 Altera Corporation
34
# SPDX-License-Identifier: MIT-0
45
#
56
proc do_create_no_pins_hps {} {
67
# create the system
78
create_system no_pins_hps
89
set_project_property BOARD {default}
9-
#set_project_property DEVICE {A5ED013BB32AE5S}
10+
#set_project_property DEVICE {A5ED013BM16AE4SCS}
1011
#set_project_property DEVICE_FAMILY {Agilex 5}
1112
set_project_property HIDE_FROM_IP_CATALOG {false}
1213
set_use_testbench_naming_pattern 0 {}
1314

1415
# add HDL parameters
1516

1617
# add the components
17-
add_component agilex_5_soc ip/no_pins_hps/agilex_5_soc.ip intel_agilex_5_soc agilex_5_soc 9.0.0
18+
add_component agilex_5_soc ip/no_pins_hps/agilex_5_soc.ip intel_agilex_5_soc agilex_5_soc 11.1.0
1819
load_component agilex_5_soc
1920
set_component_parameter_value ATB_Enable {0}
2021
set_component_parameter_value CM_Mode {N/A}
@@ -24,6 +25,7 @@ proc do_create_no_pins_hps {} {
2425
set_component_parameter_value Debug_APB_Enable {0}
2526
set_component_parameter_value ED_en_questa {1}
2627
set_component_parameter_value ED_en_riviera {0}
28+
set_component_parameter_value ED_en_sim_gen {1}
2729
set_component_parameter_value ED_en_synth_gen {0}
2830
set_component_parameter_value ED_en_vcsmx {1}
2931
set_component_parameter_value ED_en_xcelium {1}
@@ -317,7 +319,7 @@ proc do_create_no_pins_hps {} {
317319
set_component_parameter_value User1_clk_freq {200.0}
318320
set_component_parameter_value User1_clk_src_select {1}
319321
set_component_parameter_value eosc1_clk_mhz {25.0}
320-
set_component_parameter_value f2s_SMMU {0}
322+
set_component_parameter_value f2s_SMMU {1}
321323
set_component_parameter_value f2s_address_width {32}
322324
set_component_parameter_value f2s_data_width {256}
323325
set_component_parameter_value f2s_mode {ace5lite}
@@ -414,6 +416,7 @@ proc do_create_no_pins_hps {} {
414416
set_instantiation_interface_parameter_value hps2fpga maximumOutstandingTransactions {1}
415417
set_instantiation_interface_parameter_value hps2fpga maximumOutstandingWrites {1}
416418
set_instantiation_interface_parameter_value hps2fpga noRepeatedIdsBetweenSubordinates {0}
419+
set_instantiation_interface_parameter_value hps2fpga optionalAssociatedReset {false}
417420
set_instantiation_interface_parameter_value hps2fpga poison {false}
418421
set_instantiation_interface_parameter_value hps2fpga readIssuingCapability {16}
419422
set_instantiation_interface_parameter_value hps2fpga securityAttribute {false}
@@ -482,6 +485,7 @@ proc do_create_no_pins_hps {} {
482485
set_instantiation_interface_parameter_value lwhps2fpga maximumOutstandingTransactions {1}
483486
set_instantiation_interface_parameter_value lwhps2fpga maximumOutstandingWrites {1}
484487
set_instantiation_interface_parameter_value lwhps2fpga noRepeatedIdsBetweenSubordinates {0}
488+
set_instantiation_interface_parameter_value lwhps2fpga optionalAssociatedReset {false}
485489
set_instantiation_interface_parameter_value lwhps2fpga poison {false}
486490
set_instantiation_interface_parameter_value lwhps2fpga readIssuingCapability {16}
487491
set_instantiation_interface_parameter_value lwhps2fpga securityAttribute {false}
@@ -692,6 +696,7 @@ proc do_create_no_pins_hps {} {
692696
set_instantiation_interface_parameter_value f2sdram maximumOutstandingReads {1}
693697
set_instantiation_interface_parameter_value f2sdram maximumOutstandingTransactions {1}
694698
set_instantiation_interface_parameter_value f2sdram maximumOutstandingWrites {1}
699+
set_instantiation_interface_parameter_value f2sdram optionalAssociatedReset {false}
695700
set_instantiation_interface_parameter_value f2sdram poison {false}
696701
set_instantiation_interface_parameter_value f2sdram readAcceptanceCapability {16}
697702
set_instantiation_interface_parameter_value f2sdram readDataReorderingDepth {1}
@@ -778,6 +783,7 @@ proc do_create_no_pins_hps {} {
778783
set_instantiation_interface_parameter_value fpga2hps dfhParameterId {}
779784
set_instantiation_interface_parameter_value fpga2hps dfhParameterName {}
780785
set_instantiation_interface_parameter_value fpga2hps dfhParameterVersion {}
786+
set_instantiation_interface_parameter_value fpga2hps isTranslator {false}
781787
set_instantiation_interface_parameter_value fpga2hps poison {false}
782788
set_instantiation_interface_parameter_value fpga2hps readAcceptanceCapability {16}
783789
set_instantiation_interface_parameter_value fpga2hps readDataReorderingDepth {1}
@@ -833,7 +839,11 @@ proc do_create_no_pins_hps {} {
833839
add_instantiation_interface_port fpga2hps fpga2hps_rvalid rvalid 1 STD_LOGIC Output
834840
add_instantiation_interface_port fpga2hps fpga2hps_rready rready 1 STD_LOGIC Input
835841
add_instantiation_interface_port fpga2hps fpga2hps_aruser aruser 8 STD_LOGIC_VECTOR Input
842+
add_instantiation_interface_port fpga2hps fpga2hps_armmusecsid armmusecsid 1 STD_LOGIC Input
843+
add_instantiation_interface_port fpga2hps fpga2hps_armmusid armmusid 16 STD_LOGIC_VECTOR Input
836844
add_instantiation_interface_port fpga2hps fpga2hps_awuser awuser 8 STD_LOGIC_VECTOR Input
845+
add_instantiation_interface_port fpga2hps fpga2hps_awmmusecsid awmmusecsid 1 STD_LOGIC Input
846+
add_instantiation_interface_port fpga2hps fpga2hps_awmmusid awmmusid 16 STD_LOGIC_VECTOR Input
837847
add_instantiation_interface_port fpga2hps fpga2hps_arregion arregion 4 STD_LOGIC_VECTOR Input
838848
add_instantiation_interface_port fpga2hps fpga2hps_awregion awregion 4 STD_LOGIC_VECTOR Input
839849
add_instantiation_interface_port fpga2hps fpga2hps_wuser wuser 8 STD_LOGIC_VECTOR Input
@@ -906,7 +916,7 @@ proc do_create_no_pins_hps {} {
906916
add_instantiation_interface_port io96b0_to_hps io96b0_to_hps_axi4_ch0_arprot axi4_ch0_arprot 3 STD_LOGIC_VECTOR Output
907917
add_instantiation_interface_port io96b0_to_hps io96b0_to_hps_axi4_ch0_awprot axi4_ch0_awprot 3 STD_LOGIC_VECTOR Output
908918
save_instantiation
909-
add_component emif_bank3a_hps ip/no_pins_hps/emif_bank3a_hps.ip emif_io96b_hps emif_bank3a_hps 4.0.0
919+
add_component emif_bank3a_hps ip/no_pins_hps/emif_bank3a_hps.ip emif_io96b_hps emif_bank3a_hps 4.1.0
910920
load_component emif_bank3a_hps
911921
set_component_parameter_value EMIF_PROTOCOL {LPDDR4}
912922
set_component_parameter_value EMIF_REF_CLK_SHARING {0}

‎brd_altera_a5e013cs/sw_builds/build_bootloaders.sh‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
# SPDX-License-Identifier: MIT-0
66
#
77

8-
TAG_NAME="QPDS25.1.1_REL_GSRD_PR"
8+
TAG_NAME="QPDS25.3_REL_GSRD_PR"
99

1010
# change into the directory of this script
1111
cd $(dirname ${0})

‎brd_altera_a5e013cs/sw_builds/build_linux_kernel.sh‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
# SPDX-License-Identifier: MIT-0
66
#
77

8-
TAG_NAME="QPDS25.1.1_REL_GSRD_PR"
8+
TAG_NAME="QPDS25.3_REL_GSRD_PR"
99

1010
# change into the directory of this script
1111
cd $(dirname ${0})

‎brd_altera_a5e013cs/sw_builds/build_toybox.sh‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
# SPDX-License-Identifier: MIT-0
66
#
77

8-
TAG_NAME="0.8.12"
8+
TAG_NAME="0.8.13"
99

1010
# change into the directory of this script
1111
cd $(dirname ${0})

‎brd_altera_a5e065_modular_es/hw_base/a55_do_create_no_pins_hps.tcl‎

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ proc do_create_no_pins_hps {} {
1414
# add HDL parameters
1515

1616
# add the components
17-
add_component agilex_5_soc ip/no_pins_hps/agilex_5_soc.ip intel_agilex_5_soc agilex_5_soc 9.0.0
17+
add_component agilex_5_soc ip/no_pins_hps/agilex_5_soc.ip intel_agilex_5_soc agilex_5_soc 11.1.0
1818
load_component agilex_5_soc
1919
set_component_parameter_value ATB_Enable {0}
2020
set_component_parameter_value CM_Mode {N/A}
@@ -24,6 +24,7 @@ proc do_create_no_pins_hps {} {
2424
set_component_parameter_value Debug_APB_Enable {0}
2525
set_component_parameter_value ED_en_questa {1}
2626
set_component_parameter_value ED_en_riviera {0}
27+
set_component_parameter_value ED_en_sim_gen {1}
2728
set_component_parameter_value ED_en_synth_gen {0}
2829
set_component_parameter_value ED_en_vcsmx {1}
2930
set_component_parameter_value ED_en_xcelium {1}
@@ -317,7 +318,7 @@ proc do_create_no_pins_hps {} {
317318
set_component_parameter_value User1_clk_freq {200.0}
318319
set_component_parameter_value User1_clk_src_select {1}
319320
set_component_parameter_value eosc1_clk_mhz {25.0}
320-
set_component_parameter_value f2s_SMMU {0}
321+
set_component_parameter_value f2s_SMMU {1}
321322
set_component_parameter_value f2s_address_width {32}
322323
set_component_parameter_value f2s_data_width {256}
323324
set_component_parameter_value f2s_mode {ace5lite}
@@ -414,6 +415,7 @@ proc do_create_no_pins_hps {} {
414415
set_instantiation_interface_parameter_value hps2fpga maximumOutstandingTransactions {1}
415416
set_instantiation_interface_parameter_value hps2fpga maximumOutstandingWrites {1}
416417
set_instantiation_interface_parameter_value hps2fpga noRepeatedIdsBetweenSubordinates {0}
418+
set_instantiation_interface_parameter_value hps2fpga optionalAssociatedReset {false}
417419
set_instantiation_interface_parameter_value hps2fpga poison {false}
418420
set_instantiation_interface_parameter_value hps2fpga readIssuingCapability {16}
419421
set_instantiation_interface_parameter_value hps2fpga securityAttribute {false}
@@ -482,6 +484,7 @@ proc do_create_no_pins_hps {} {
482484
set_instantiation_interface_parameter_value lwhps2fpga maximumOutstandingTransactions {1}
483485
set_instantiation_interface_parameter_value lwhps2fpga maximumOutstandingWrites {1}
484486
set_instantiation_interface_parameter_value lwhps2fpga noRepeatedIdsBetweenSubordinates {0}
487+
set_instantiation_interface_parameter_value lwhps2fpga optionalAssociatedReset {false}
485488
set_instantiation_interface_parameter_value lwhps2fpga poison {false}
486489
set_instantiation_interface_parameter_value lwhps2fpga readIssuingCapability {16}
487490
set_instantiation_interface_parameter_value lwhps2fpga securityAttribute {false}
@@ -692,6 +695,7 @@ proc do_create_no_pins_hps {} {
692695
set_instantiation_interface_parameter_value f2sdram maximumOutstandingReads {1}
693696
set_instantiation_interface_parameter_value f2sdram maximumOutstandingTransactions {1}
694697
set_instantiation_interface_parameter_value f2sdram maximumOutstandingWrites {1}
698+
set_instantiation_interface_parameter_value f2sdram optionalAssociatedReset {false}
695699
set_instantiation_interface_parameter_value f2sdram poison {false}
696700
set_instantiation_interface_parameter_value f2sdram readAcceptanceCapability {16}
697701
set_instantiation_interface_parameter_value f2sdram readDataReorderingDepth {1}
@@ -778,6 +782,7 @@ proc do_create_no_pins_hps {} {
778782
set_instantiation_interface_parameter_value fpga2hps dfhParameterId {}
779783
set_instantiation_interface_parameter_value fpga2hps dfhParameterName {}
780784
set_instantiation_interface_parameter_value fpga2hps dfhParameterVersion {}
785+
set_instantiation_interface_parameter_value fpga2hps isTranslator {false}
781786
set_instantiation_interface_parameter_value fpga2hps poison {false}
782787
set_instantiation_interface_parameter_value fpga2hps readAcceptanceCapability {16}
783788
set_instantiation_interface_parameter_value fpga2hps readDataReorderingDepth {1}
@@ -833,7 +838,11 @@ proc do_create_no_pins_hps {} {
833838
add_instantiation_interface_port fpga2hps fpga2hps_rvalid rvalid 1 STD_LOGIC Output
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add_instantiation_interface_port fpga2hps fpga2hps_rready rready 1 STD_LOGIC Input
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add_instantiation_interface_port fpga2hps fpga2hps_aruser aruser 8 STD_LOGIC_VECTOR Input
841+
add_instantiation_interface_port fpga2hps fpga2hps_armmusecsid armmusecsid 1 STD_LOGIC Input
842+
add_instantiation_interface_port fpga2hps fpga2hps_armmusid armmusid 16 STD_LOGIC_VECTOR Input
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add_instantiation_interface_port fpga2hps fpga2hps_awuser awuser 8 STD_LOGIC_VECTOR Input
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add_instantiation_interface_port fpga2hps fpga2hps_awmmusecsid awmmusecsid 1 STD_LOGIC Input
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add_instantiation_interface_port fpga2hps fpga2hps_awmmusid awmmusid 16 STD_LOGIC_VECTOR Input
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add_instantiation_interface_port fpga2hps fpga2hps_arregion arregion 4 STD_LOGIC_VECTOR Input
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add_instantiation_interface_port fpga2hps fpga2hps_awregion awregion 4 STD_LOGIC_VECTOR Input
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add_instantiation_interface_port fpga2hps fpga2hps_wuser wuser 8 STD_LOGIC_VECTOR Input
@@ -906,7 +915,7 @@ proc do_create_no_pins_hps {} {
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add_instantiation_interface_port io96b0_to_hps io96b0_to_hps_axi4_ch0_arprot axi4_ch0_arprot 3 STD_LOGIC_VECTOR Output
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add_instantiation_interface_port io96b0_to_hps io96b0_to_hps_axi4_ch0_awprot axi4_ch0_awprot 3 STD_LOGIC_VECTOR Output
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save_instantiation
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add_component emif_bank3a_hps ip/no_pins_hps/emif_bank3a_hps.ip emif_io96b_hps emif_bank3a_hps 4.0.0
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add_component emif_bank3a_hps ip/no_pins_hps/emif_bank3a_hps.ip emif_io96b_hps emif_bank3a_hps 4.1.0
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load_component emif_bank3a_hps
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set_component_parameter_value EMIF_PROTOCOL {DDR4_COMP}
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set_component_parameter_value EMIF_REF_CLK_SHARING {0}

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