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rodfrazer-intelrodfrazer-intel
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Update to QPDS 25.1.1 tools release
This is a significant update to all hardware and software objects within this repo as they are all updated to build under the QPDS 25.1.1 tools environment. Some of the more notable changes are listed below: The following IP cores are updated in the 25.1.1 tools: intel_agilex_5_soc instance 9.0.0 emif_io96b_hps 4.0.0 altera_axi_bridge 19.9.5 The 25.1.1 tools require all pin locations to be defined in the QSF in order to allow SOF file generation. All boards have been updated with a full set of pin assignments. Added HPS EMIF ECC support for Altera 065 premium dev kit and modular dev kit. Added the brd_altera_a5e013cs board which supports the production Agilex* 5 FPGA E-Series 013B Development Kit. u-boot-socfpga, arm-trusted-firmware and linux-socfpga are updated to the latest tag, QPDS25.1.1_REL_GSRD_PR toybox remains at the latest tag, 0.8.12 Signed-off-by: Rod Frazer <rod.frazer@altera.com>
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‎README.md‎

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@@ -7,9 +7,9 @@
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- **title**: agilex5-demo-hps2fpga-interfaces
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- **source**: GitHub
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- **family**: Agilex 5
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- **quartus_version**: Version 25.1.0 Build 129 03/26/2025 SC Pro Edition
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- **quartus_version**: Version 25.1.1 Build 125 07/31/2025 SC Pro Edition
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- **devkit**: Agilex 5 FPGA E-Series 065B Premium Development Kit, and others
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- **device_part**: A5ED065BB32AE5SR0, A5ED065BB32AE4SR0, A5ED065BB32AE6SR0
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- **device_part**: A5ED065BB32AE5SR0, A5ED065BB32AE4SR0, A5ED065BB32AE6SR0, A5ED013BM16AE4SCS
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- **description**: Agilex 5 HPS-to-FPGA interfaces demos.
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- **rich_description**: This project is a demonstration and evaluation example that shows how users can implement and interact with the various hardware interfaces between the Hard Processing System (SoC) and FPGA fabric on the Agilex 5 FPGA device family.
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- **url**: https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces
@@ -29,6 +29,7 @@ The project build instructions are documented [**here**](./documentation/17_buil
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| :--- | :--- |
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| brd_altera_a5e065_premium_es | **Company:** Altera Corporation<br>**Board Name:** Agilex* 5 FPGA E-Series 065B Premium Development Kit<br>**OPN:** DK-A5E065BB32AES1<br>**Comment:** ES device |
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| brd_altera_a5e065_modular_es | **Company:** Altera Corporation<br>**Board Name:** Agilex* 5 FPGA E-Series 065B Modular Development Kit<br>**OPN:** MK-A5E065BB32AES1<br>**Comment:** ES device |
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| brd_altera_a5e013cs | **Company:** Altera Corporation<br>**Board Name:** Agilex* 5 FPGA E-Series 013B Development Kit<br>**OPN:** DK-A5E013BM16AEA<br>**Comment:** Production device |
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| brd_arrow_axe5_eagle_es | **Company:** Arrow Electronics, Inc.<br>**Board Name:** Arrow AXE5-Eagle Development Platform<br>**OPN:** AXE5-EAGLE-ES<br>**Comment:** ES device |
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| brd_criticallink_mitysbc_es | **Company:** Critical Link, LLC<br>**Board Name:** MitySBC-A5E Single Board Computer<br>**OPN:** A5ED-B9-C7F-RC-SBC-X<br>**Comment:** ES device |
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| brd_macnica_sulfur_es_125 | **Company:** Macnica, Inc.<br>**Board Name:** Macnica Mpression Sulfur Kit / Type A<br>**OPN:** ALTSULFUR_A5ED065B_E5_ES0_typeA<br>**Comment:** ES device - 125MHz SDM_OSC_CLK |

‎brd_altera_a5e013cs/hw_base/a55_do_create_no_pins_hps.tcl‎

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‎brd_altera_a5e013cs/hw_base/a76_do_create_no_pins_hps.tcl‎

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‎brd_altera_a5e013cs/hw_base/create_quartus_project.tcl‎

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#
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# SPDX-FileCopyrightText: Copyright (C) 2025 Altera Corporation
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# SPDX-License-Identifier: MIT-0
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#
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#
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# This script is created by first going into Quartus and select the menu:
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# Project -> Organize Quartus Prime Settings File
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#
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# Then export the project to TCL:
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# Project -> Generate Tcl File for Project...
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#
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# We then take that TCL file and reformat it for our needs. We discard ancilary
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# settings that are of no real use and we remove all .qsys and .ip references
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# because we will restore those into future project creations as we reconstruct
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# the project from raw source.
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#
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# The default format of the pin assignments may or may not be desirable, it will
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# list all pin locations first followed by all pin instance assignments. If we
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# wish to sort this list placing all assignments for a given pin together, we
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# can do this:
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#
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# Duplicate the original generated TCL file and call it pins_only.tcl. Edit the
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# file to remove all entries but the pin assignments. Also remove any entity
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# references at the ends of any lines, each line should end with the
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# "-to <target>" value. Then we can run this command line to sort the pin
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# assignments:
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#
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# []$ awk '{print $NF,$0}' pins_only.tcl | sort -s -k 1,1 | cut -f2- -d' ' > sorted_pins_only.tcl
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#
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package require ::quartus::project
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set PROJECT_NAME "no_pins_top"
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if [project_exists $PROJECT_NAME] {
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post_message -type error "project already exists..."
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post_message -type error "'$PROJECT_NAME'"
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qexit -error
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}
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project_new $PROJECT_NAME
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name VERILOG_FILE ../hw_base/no_pins_top.v
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
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set_global_assignment -name FAMILY "Agilex 5"
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set_global_assignment -name TOP_LEVEL_ENTITY no_pins_top
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set_global_assignment -name BOARD default
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set_global_assignment -name DEVICE A5ED013BM16AE4SCS
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
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set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ
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set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_100MHZ
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set_global_assignment -name USE_HPS_COLD_RESET SDM_IO10
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set_global_assignment -name USE_CONF_DONE SDM_IO16
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set_global_assignment -name USE_INIT_DONE SDM_IO0
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set_global_assignment -name SDM_DIRECT_TO_FACTORY_IMAGE SDM_IO13
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set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
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set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
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set_global_assignment -name NUMBER_OF_SLAVE_DEVICE 2
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set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
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set_global_assignment -name HPS_DAP_SPLIT_MODE "SDM PINS"
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set_global_assignment -name HPS_DAP_NO_CERTIFICATE on
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set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name POWER_APPLY_THERMAL_MARGIN ADDITIONAL
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set_global_assignment -name STRATIX_JTAG_USER_CODE 66666666
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set_global_assignment -name USE_CHECKSUM_AS_USERCODE OFF
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set_global_assignment -name HPS_INITIALIZATION "HPS FIRST"
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set_global_assignment -name QSPI_OWNERSHIP HPS
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set_global_assignment -name INI_VARS "asm_enable_advanced_devices=on"
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set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
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set_location_assignment PIN_C2 -to emif_hps_emif_mem_0_mem_ca[0]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_ca[0]
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set_location_assignment PIN_D3 -to emif_hps_emif_mem_0_mem_ca[1]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_ca[1]
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set_location_assignment PIN_C3 -to emif_hps_emif_mem_0_mem_ca[2]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_ca[2]
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set_location_assignment PIN_B3 -to emif_hps_emif_mem_0_mem_ca[3]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_ca[3]
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set_location_assignment PIN_A6 -to emif_hps_emif_mem_0_mem_ca[4]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_ca[4]
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set_location_assignment PIN_B5 -to emif_hps_emif_mem_0_mem_ca[5]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_ca[5]
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set_location_assignment PIN_E10 -to emif_hps_emif_mem_0_mem_ck_c
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_ck_c
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set_location_assignment PIN_A4 -to emif_hps_emif_mem_0_mem_cke
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_cke
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set_location_assignment PIN_E9 -to emif_hps_emif_mem_0_mem_ck_t
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_ck_t
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set_location_assignment PIN_C7 -to emif_hps_emif_mem_0_mem_cs
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_cs
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set_location_assignment PIN_L7 -to emif_hps_emif_mem_0_mem_dmi[0]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dmi[0]
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set_location_assignment PIN_K5 -to emif_hps_emif_mem_0_mem_dmi[1]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dmi[1]
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set_location_assignment PIN_D13 -to emif_hps_emif_mem_0_mem_dmi[2]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dmi[2]
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set_location_assignment PIN_B11 -to emif_hps_emif_mem_0_mem_dmi[3]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dmi[3]
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set_location_assignment PIN_H6 -to emif_hps_emif_mem_0_mem_dq[0]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[0]
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set_location_assignment PIN_H7 -to emif_hps_emif_mem_0_mem_dq[1]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[1]
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set_location_assignment PIN_M3 -to emif_hps_emif_mem_0_mem_dq[10]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[10]
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set_location_assignment PIN_L4 -to emif_hps_emif_mem_0_mem_dq[11]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[11]
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set_location_assignment PIN_M4 -to emif_hps_emif_mem_0_mem_dq[12]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[12]
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set_location_assignment PIN_G4 -to emif_hps_emif_mem_0_mem_dq[13]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[13]
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set_location_assignment PIN_H3 -to emif_hps_emif_mem_0_mem_dq[14]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[14]
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set_location_assignment PIN_H5 -to emif_hps_emif_mem_0_mem_dq[15]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[15]
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set_location_assignment PIN_D15 -to emif_hps_emif_mem_0_mem_dq[16]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[16]
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set_location_assignment PIN_C13 -to emif_hps_emif_mem_0_mem_dq[17]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[17]
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set_location_assignment PIN_C10 -to emif_hps_emif_mem_0_mem_dq[18]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[18]
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set_location_assignment PIN_D10 -to emif_hps_emif_mem_0_mem_dq[19]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[19]
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set_location_assignment PIN_G5 -to emif_hps_emif_mem_0_mem_dq[2]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[2]
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set_location_assignment PIN_C8 -to emif_hps_emif_mem_0_mem_dq[20]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[20]
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set_location_assignment PIN_D9 -to emif_hps_emif_mem_0_mem_dq[21]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[21]
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set_location_assignment PIN_D14 -to emif_hps_emif_mem_0_mem_dq[22]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[22]
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set_location_assignment PIN_C15 -to emif_hps_emif_mem_0_mem_dq[23]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[23]
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set_location_assignment PIN_A8 -to emif_hps_emif_mem_0_mem_dq[24]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[24]
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set_location_assignment PIN_B8 -to emif_hps_emif_mem_0_mem_dq[25]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[25]
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set_location_assignment PIN_A9 -to emif_hps_emif_mem_0_mem_dq[26]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[26]
142+
set_location_assignment PIN_B9 -to emif_hps_emif_mem_0_mem_dq[27]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[27]
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set_location_assignment PIN_B13 -to emif_hps_emif_mem_0_mem_dq[28]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[28]
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set_location_assignment PIN_A13 -to emif_hps_emif_mem_0_mem_dq[29]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[29]
148+
set_location_assignment PIN_G6 -to emif_hps_emif_mem_0_mem_dq[3]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[3]
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set_location_assignment PIN_B14 -to emif_hps_emif_mem_0_mem_dq[30]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[30]
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set_location_assignment PIN_A14 -to emif_hps_emif_mem_0_mem_dq[31]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[31]
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set_location_assignment PIN_M6 -to emif_hps_emif_mem_0_mem_dq[4]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[4]
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set_location_assignment PIN_N5 -to emif_hps_emif_mem_0_mem_dq[5]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[5]
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set_location_assignment PIN_M5 -to emif_hps_emif_mem_0_mem_dq[6]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[6]
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set_location_assignment PIN_L6 -to emif_hps_emif_mem_0_mem_dq[7]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[7]
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set_location_assignment PIN_L3 -to emif_hps_emif_mem_0_mem_dq[8]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[8]
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set_location_assignment PIN_J5 -to emif_hps_emif_mem_0_mem_dq[9]
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set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dq[9]
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set_location_assignment PIN_J7 -to emif_hps_emif_mem_0_mem_dqs_c[0]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dqs_c[0]
168+
set_location_assignment PIN_J3 -to emif_hps_emif_mem_0_mem_dqs_c[1]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dqs_c[1]
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set_location_assignment PIN_C11 -to emif_hps_emif_mem_0_mem_dqs_c[2]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dqs_c[2]
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set_location_assignment PIN_A11 -to emif_hps_emif_mem_0_mem_dqs_c[3]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dqs_c[3]
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set_location_assignment PIN_K7 -to emif_hps_emif_mem_0_mem_dqs_t[0]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dqs_t[0]
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set_location_assignment PIN_J4 -to emif_hps_emif_mem_0_mem_dqs_t[1]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dqs_t[1]
178+
set_location_assignment PIN_D12 -to emif_hps_emif_mem_0_mem_dqs_t[2]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dqs_t[2]
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set_location_assignment PIN_B10 -to emif_hps_emif_mem_0_mem_dqs_t[3]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_dqs_t[3]
182+
set_location_assignment PIN_E15 -to emif_hps_emif_mem_0_mem_reset_n
183+
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to emif_hps_emif_mem_0_mem_reset_n
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set_location_assignment PIN_E14 -to emif_hps_emif_oct_0_oct_rzqin
185+
set_instance_assignment -name IO_STANDARD "1.1-V" -to emif_hps_emif_oct_0_oct_rzqin
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set_location_assignment PIN_A7 -to emif_hps_emif_ref_clk_0_clk
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set_location_assignment PIN_B6 -to "emif_hps_emif_ref_clk_0_clk(n)"
188+
set_instance_assignment -name IO_STANDARD "1.8-V" -to hps_osc_clk
189+
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hps_uart0_RX
190+
set_location_assignment PIN_F24 -to hps_uart0_RX
191+
set_instance_assignment -name IO_STANDARD "1.8-V" -to hps_uart0_RX
192+
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to hps_uart0_TX
193+
set_location_assignment PIN_C27 -to hps_uart0_TX
194+
set_instance_assignment -name IO_STANDARD "1.8-V" -to hps_uart0_TX
195+
196+
export_assignments
197+
198+
project_close
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‎brd_altera_a5e013cs/hw_base/custom_ip.ipx‎

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<!--
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SPDX-FileCopyrightText: Copyright (C) 2024 Intel Corporation
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SPDX-FileCopyrightText: Copyright (C) 2025 Altera Corporation
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SPDX-License-Identifier: MIT-0
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-->
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<library>
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<path path="../../custom_ip/**/*" >
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<tag2 key="COMPONENT_IN_PROJECT" value="true" />
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</path>
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<plugin
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name="DDR4-1600L_800MHz_CL12_alloff_component_1CS_DDP_32Gb_2Gx16.qprs"
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file="../hw_base/DDR4-1600L_800MHz_CL12_alloff_component_1CS_DDP_32Gb_2Gx16.qprs"
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displayName="DDR4-1600L_800MHz_CL12_alloff_component_1CS_DDP_32Gb_2Gx16.qprs"
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version="0.0"
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description=""
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tags=""
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categories=""
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type="com.altera.sopcmodel.util.IElementPresetList"
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subtype=""
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factory="PresetFactory">
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<tag2 key="PRESET_TYPE" value="emif_ph2_phy_arch_fp" />
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</plugin>
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</library>

‎brd_altera_a5e013cs/hw_base/no_pins_top.v‎

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/*
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* SPDX-FileCopyrightText: Copyright (C) 2024 Intel Corporation
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* SPDX-FileCopyrightText: Copyright (C) 2025 Altera Corporation
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* SPDX-License-Identifier: MIT-0
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*/
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`timescale 1ns/10ps
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module no_pins_top (
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input hps_osc_clk,
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output hps_uart0_TX,
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input hps_uart0_RX,
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output wire emif_hps_emif_mem_0_mem_ck_t,
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output wire emif_hps_emif_mem_0_mem_ck_c,
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output wire emif_hps_emif_mem_0_mem_cke,
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output wire emif_hps_emif_mem_0_mem_reset_n,
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input wire emif_hps_emif_oct_0_oct_rzqin,
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input wire emif_hps_emif_ref_clk_0_clk,
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inout wire [ 3:0] emif_hps_emif_mem_0_mem_dqs_t,
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inout wire [ 3:0] emif_hps_emif_mem_0_mem_dqs_c,
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inout wire [31:0] emif_hps_emif_mem_0_mem_dq,
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output wire emif_hps_emif_mem_0_mem_cs,
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output wire [ 5:0] emif_hps_emif_mem_0_mem_ca,
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inout wire [ 3:0] emif_hps_emif_mem_0_mem_dmi
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);
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no_pins_pd_top hps_system (
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.hps_io_hps_osc_clk (hps_osc_clk),
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.hps_io_uart0_tx (hps_uart0_TX),
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.hps_io_uart0_rx (hps_uart0_RX),
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.emif_bank3a_hps_mem_0_mem_cs (emif_hps_emif_mem_0_mem_cs),
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.emif_bank3a_hps_mem_0_mem_ca (emif_hps_emif_mem_0_mem_ca),
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.emif_bank3a_hps_mem_0_mem_cke (emif_hps_emif_mem_0_mem_cke),
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.emif_bank3a_hps_mem_0_mem_dq (emif_hps_emif_mem_0_mem_dq),
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.emif_bank3a_hps_mem_0_mem_dqs_t (emif_hps_emif_mem_0_mem_dqs_t),
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.emif_bank3a_hps_mem_0_mem_dqs_c (emif_hps_emif_mem_0_mem_dqs_c),
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.emif_bank3a_hps_mem_0_mem_dmi (emif_hps_emif_mem_0_mem_dmi),
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.emif_bank3a_hps_mem_ck_0_mem_ck_t (emif_hps_emif_mem_0_mem_ck_t),
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.emif_bank3a_hps_mem_ck_0_mem_ck_c (emif_hps_emif_mem_0_mem_ck_c),
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.emif_bank3a_hps_mem_reset_n_mem_reset_n (emif_hps_emif_mem_0_mem_reset_n),
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.emif_bank3a_hps_oct_0_oct_rzqin (emif_hps_emif_oct_0_oct_rzqin),
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.emif_bank3a_hps_ref_clk_clk (emif_hps_emif_ref_clk_0_clk)
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);
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endmodule

‎brd_altera_a5e013cs/images/build_images.sh‎

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#!/bin/bash
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#
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# SPDX-FileCopyrightText: Copyright (C) 2024 Intel Corporation
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# SPDX-License-Identifier: MIT-0
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#
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# change into the directory of this script
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cd $(dirname ${0})
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IMAGE_BUILD_SCRIPTS="
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../../common_images/build_demos_fit_image.sh
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../../common_images/build_jic_image.sh
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../../common_images/create_attribution.sh
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../../common_images/fit_no-pins-demos.its
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../../common_images/fit_lzma-no-pins-demos.its
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../../common_images/jic_no-pins-demos.pfg
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"
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for NEXT in ${IMAGE_BUILD_SCRIPTS:?}
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do
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[ -f "$(basename "${NEXT:?}")" ] || {
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cp -s -t ./ "${NEXT:?}" || { echo "ERROR" ; exit 1 ; }
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echo "Created symbolic link for '$(basename ${NEXT:?})'"
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}
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done
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sed -i.bak -e "/flash_loader/ s/A5ED065BB32AR0/A5ED013BM16A/" jic_no-pins-demos.pfg \
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|| { echo "ERROR" ; exit 1 ; }
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./build_jic_image.sh || { echo "ERROR" ; exit 1 ; }
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‎brd_altera_a5e013cs/init_hw_build_scripts.sh‎

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#!/bin/bash
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#
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# SPDX-FileCopyrightText: Copyright (C) 2024 Intel Corporation
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# SPDX-License-Identifier: MIT-0
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#
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# change into the directory of this script
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cd $(dirname ${0})
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cp -s \
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-t ./ \
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../common_build_scripts/build_hw.sh \
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../common_build_scripts/check_hw_build.sh \
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../common_build_scripts/create_bitstreams.sh \
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../common_build_scripts/hw_build_dirs.src \
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|| { echo "ERROR" ; exit 1 ; }
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# source the hardware build directories variable declaration
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. ./hw_build_dirs.src
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for NEXT_BUILD_DIR in ${HW_BUILD_DIRECTORIES:?}
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do
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echo "Creating hardware directory: '${NEXT_BUILD_DIR:?}'"
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mkdir "${NEXT_BUILD_DIR:?}" && \
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ln -s \
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../../common_build_scripts/uart0_init_proj.sh \
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./${NEXT_BUILD_DIR:?}/init_proj.sh \
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|| { echo "ERROR" ; exit 1 ; }
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done
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